Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2009-04-02
2010-06-29
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S041000
Reexamination Certificate
active
07746108
ABSTRACT:
Integrated circuits having a compute-centric architecture. An integrated circuit may include an array of interconnected substantially similar logic blocks, each including a multiplier circuit and a lookup table circuit. The multiplier circuit has first and second inputs coupled to first and second data inputs of the logic block, and an output, and may include a non-uniform array of sub-circuits. The lookup table circuit has a first input coupled to a third data input of the logic block, a second input coupled to the output of the multiplier circuit, and an output coupled to a data output of the logic block. The multiplier circuits in adjacent logic blocks may be coupled together via a multi-bit partial product bus. Optional storage elements store the first and second inputs and the output of the multiplier circuit, the partial product bus, and the output of the lookup table circuit.
REFERENCES:
patent: 5126975 (1992-06-01), Handy et al.
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5367209 (1994-11-01), Hauck et al.
patent: 5513132 (1996-04-01), Williams
patent: 5999961 (1999-12-01), Manohar et al.
patent: 6140836 (2000-10-01), Fujii et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6184712 (2001-02-01), Wittig et al.
patent: 6208163 (2001-03-01), Wittig et al.
patent: 6225827 (2001-05-01), Fujii et al.
patent: 6308229 (2001-10-01), Masteller
patent: 6320418 (2001-11-01), Fujii et al.
patent: 6369614 (2002-04-01), Ridgway
patent: 6476643 (2002-11-01), Hugues et al.
patent: 6486709 (2002-11-01), Sutherland et al.
patent: 6522170 (2003-02-01), Durham et al.
patent: 6531897 (2003-03-01), Milshtein et al.
patent: 6590424 (2003-07-01), Singh et al.
patent: 6708193 (2004-03-01), Zeng
patent: 6850092 (2005-02-01), Chelcea et al.
patent: 6949954 (2005-09-01), Nystrom et al.
patent: 6958627 (2005-10-01), Singh et al.
patent: 6959315 (2005-10-01), Chren, Jr.
patent: 6990510 (2006-01-01), Friend et al.
patent: 7050324 (2006-05-01), Cummings et al.
patent: 7053665 (2006-05-01), Singh et al.
patent: 7157934 (2007-01-01), Teifel et al.
patent: 7196543 (2007-03-01), Young et al.
patent: 7202698 (2007-04-01), Bauer et al.
patent: 7274211 (2007-09-01), Simkins et al.
patent: 7308627 (2007-12-01), Schultz et al.
patent: 7352204 (2008-04-01), Frisch
patent: 7375552 (2008-05-01), Young et al.
patent: 7417456 (2008-08-01), Verma et al.
patent: 7467175 (2008-12-01), Simkins et al.
patent: 7467177 (2008-12-01), Simkins et al.
patent: 7472155 (2008-12-01), Simkins et al.
patent: 7480690 (2009-01-01), Simkins et al.
patent: 7504851 (2009-03-01), Manohar et al.
patent: 7505304 (2009-03-01), Manohar et al.
patent: 7538579 (2009-05-01), Schleicher et al.
patent: 7609085 (2009-10-01), Schmit et al.
patent: 7652498 (2010-01-01), Hutchings et al.
patent: 2003/0055852 (2003-03-01), Wojko
patent: 2004/0044716 (2004-03-01), Colon-Bonet
patent: 2005/0127944 (2005-06-01), Lewis et al.
patent: 2005/0144210 (2005-06-01), Simkins et al.
patent: 2006/0164119 (2006-07-01), Nowak-Leijten
patent: 2006/0190516 (2006-08-01), Simkins et al.
patent: 2006/0195496 (2006-08-01), Vadi et al.
patent: 2006/0206557 (2006-09-01), Wong et al.
patent: 2006/0212499 (2006-09-01), New et al.
patent: 2006/0230092 (2006-10-01), Ching et al.
patent: 2006/0230093 (2006-10-01), New et al.
patent: 2006/0230094 (2006-10-01), Simkins et al.
patent: 2006/0230095 (2006-10-01), Simkins et al.
patent: 2006/0230096 (2006-10-01), Thendean et al.
patent: 2006/0288069 (2006-12-01), Simkins et al.
patent: 2006/0288070 (2006-12-01), Vadi et al.
patent: 2006/0291302 (2006-12-01), Seto et al.
patent: 2007/0126474 (2007-06-01), Chang et al.
patent: 2007/0252617 (2007-11-01), Lewis et al.
patent: 2007/0256038 (2007-11-01), Manohar
patent: 2008/0168407 (2008-07-01), Manohar
patent: 2009/0153188 (2009-06-01), Vorbach et al.
patent: 2009/0289660 (2009-11-01), Ngai et al.
U.S. Appl. No. 12/417,007, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,010, filed Apr. 2, 2009, Young.
U.S. Appl. No. 12/417,012, filed Apr. 2, 2009, Young.
U.S. Appl. No. 12/417,015, filed Apr. 2, 2009, Young.
U.S. Appl. No. 12/417,018, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,020, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,023, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,024, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,033, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,036, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,040, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,043, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,046, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,048, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,051, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,054, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,057, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/174,905, filed Jul. 17, 2008, Young.
U.S. Appl. No. 12/174,926, filed July 17, 2008, Young.
U.S. Appl. No. 12/174,945, filed July 17, 2008, Young.
U.S. Appl. No. 12/174,956, filed July 17, 2008, Young.
U.S. Appl. No. 12/174,972, filed July 17, 2008, Young et al.
Achronix Semiconductor Corp.,Introduction to Achronix FPGAs, WP001 Rev. 1.6, Aug. 7, 2008, pp. 1-7, available from Achronix Semiconductor Corp., San Jose, California, USA.
Achronix Semiconductor Corp.,Speedster FPGA Family, PB001 v3.5, copyright 2008, pp. 1-2, available from Achronix Semiconductor Corp., San Jose, California, USA.
Asato, Creighton et al., “A Data-Path Multiplier with Automatic Insertion of Pipeline Stages ”IEEE Journal of Solid-State Circuits, Apr. 1990, pp. 383-387, vol. 25, No. 2.
Borriello, F. et al., “The Triptych FPGA Architecture,”IEEE Transactions on Very Large Scale Integration(VLSI)Systems, Dec. 1990, pp. 491-501, vol. 3, No. 4.
Callaway, Thomas K., “Optimizing Arithmetic Elements for Signal Processing,”Proc. of the 1992 Workshop on VLSI Signal Processing, Oct. 28-30, 1992, vol. V, pp. 99-100, Napa Valley, California, USA.
Habibi, I. et al., “Fast Multipliers,”IEEE Transactions on Computers, Feb. 1970, pp. 153-157, vol. C-19, Issue 2.
Halfhill, Tom, “Ambric's New Parallel Processor,”Microprocessor Report, Oct. 10, 2006, pp. 1-9, available from In-Stat, 2055 Gateway Place, San Jose, California, USA, or http://www.mpronline.com.
Hauck, Scott et al., “Montage: An FPGA for Synchronous and Asynchronous Circuits ”Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping, 1999, pp. 44-51, publ. by Springer Verlag, Berlin, Germany.
Hauck, Scott et al., “An FPGA for Implementing Asynchronous Circuits ”IEEE Design and Test of Computers, Fall 1994, pp. 60-69, vol. 11, No. 3.
Hauck, Scott, “Asynchronous Design Methodologies: An Overview,”Proc. of the IEEE, Jan. 1995, pp. 69-93, vol. 83, No. 1.
Hauser, John,The Garp Architecture, Oct. 1997, pp. 1-56, University of California at Berkeley, USA.
Huang, Randy,Hardware-Assisted Fast Routing for Runtime Reconfiqurable Computing, Fall 2004, pp. 1-43, dissertation submitted to University of California at Berkeley, USA.
Jain, Surendra K. et al., “Efficient Semisystolic Architectures for Finite-Field Arithmetic”IEEE Transactions on Very Large Scale Integration(VLSI)Systems, March 1998, pp. 101-113, vol. 6, No. 1.
Maden, B. et al., “Parallel Architectures for High Speed Multipliers,”Proc. of the 1989 IEEE International Symposium on Circuits and Systems, May 8-11, 1989, pp. 142-145, Portland, Oregon.
Martin, Alain et al., “The Design of an Asynchronous Microprocessor,”Proc. Decennial Caltech Conference on VLSI, Mar. 20-22, 1989, pp. 1-23.
Meier, Pascal C. H. et al., “Exploring Multiplier Architecture and Layout for Low Power,”Proc. of the 1996 IEEE Custom Integrated Circuits Conference, May 5-8, 1996, pp. 513-516.
Muhammad, Khurram et al., “Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design,”Proc. of the 199
Gaide Brian C.
Young Steven P.
Cartier Lois D.
Tran Anh Q
Xilinx , Inc.
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