Computational field programmable architecture

Details Computational field programmable architecture Computational field programmable architecture

1998-05-13

2000-10-31

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, 326 47, H03K 19177, H03K 19173

Patent

active

061408395

ABSTRACT:
A computational field programable architecture targeted for compute intensive applications. The architecture is hierarchical and includes, for implementation of data path circuits, clusters of programable logic blocks that are designed to provide area-efficient realization of common arithmetic structures such as adders, subtracters and multipliers. The architecture includes a LUTb cluster for implementing the control part of a circuit. The programable logic blocks each include a stack of programable bit-slice logic elements each having 2 data inputs and a single data output, and a 1-bit full adder circuit. The bit slice logic elements allow bit-wise logic operations to be carried out and the programable logic blocks also include comparator logic to enable comparison operations to be performed. The bit slice logic elements each include a DFF at their output, and the DFFs in a programable logic blocks can be combined to form a register. The inputs of each of the programable logic blocks are connected to cluster level tracks through a partially populated crossbar.

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Carl Ebeling, Darren C. Cronquist and Paul Franklin, "RaPiD--Reconfigurable Pipelined Datapath", FPL '96: The 6th International Workshop on Field Programmable Logic and Applications, pp. 126-135.Springer--Verlag, 1996.
Don Cherepacha and David Lewis, "DP-FPGA: An FPGA Architecture Optimized for Datapaths", pp. 1 to 25, (Published in VLSI & Designs 1996 vol. 4, pp. 329-343).

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