Compression circuit for testing a memory device

Details Compression circuit for testing a memory device Compression circuit for testing a memory device

2006-11-14

2006-11-14

Torres, Joseph (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S732000, C714S733000

Reexamination Certificate

active

07137050

ABSTRACT:
An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal.

REFERENCES:
patent: 5774477 (1998-06-01), Ke
patent: 6311299 (2001-10-01), Bunker
patent: 6735729 (2004-05-01), Merritt et al.

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