Compression circuit for testing a memory device

Details Compression circuit for testing a memory device Compression circuit for testing a memory device

1999-08-18

2004-05-11

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06735729

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the testing of memory devices, and more particularly to the testing of memory devices using a compression circuit.
2. Description of the Related Art
Memory devices, such as a synchronous dynamic random access memory (SDRAM), are being developed with ever-increasing densities. During the manufacturing process, the memory device is tested to verify proper operation. If improperly functioning cells are identified, the memory device may be repaired or discarded, depending on the number, type, and arrangement of faulty memory cells. Also, if a sample of memory devices is tested and the individual memory devices are found to have faults in common locations, certain stages in the manufacturing process may be examined and/or altered to correct possible systemic defects.
As the density of memory devices increases, the time required to test the devices also increases. Compression circuits have been developed to simultaneously test blocks of memory cells and provide information regarding the success or failure of the test. A test using a compression circuit indicates that one of the cells in the block of cells is faulty. Further testing is required to identify the specific cell. Typically, the further test involves a time consuming cell-by-cell test to identify the faulty cell.
FIG. 1
illustrates a logic diagram of a prior art compression circuit
10
. The compression circuit
10
of
FIG. 1
receives sixteen input lines, D
1
-D
16
(e.g., I/O lines) and provides an output based on the success of the test. The compression circuit
10
includes a first portion
14
adapted to provide an indication that all logic ones are present on the input lines D
1
-D
16
, and a second portion
16
adapted to provide an indication that all logic zeros are present on the input lines D
1
-D
16
. If any of the input lines D
1
-D
16
on the first portion
14
receive a logic “0”, the first portion
14
of the compression circuit
10
will indicate a fail condition. Likewise, if any of the input lines on the second portion
16
receives a logic “1”, the second portion
14
of the compression circuit
10
will indicate a fail condition.
The first portion
14
of the compression circuit
10
includes an arrangement of NAND gates
18
, NOR gates
20
, and an inverter
22
that collectively perform a logical 16-bit wide NAND function. Conversely, the second portion
16
of the compression circuit
10
includes NOR gates
24
, NAND gates
26
, and an inverter
28
that collectively perform a logical 16-bit wide NOR function. The compression ratio of the compression circuit
10
may be altered by increasing or decreasing the number of cascaded rows of NAND gates
18
,
24
and NOR gates
20
,
26
.
The compression circuit
10
also includes an output circuit
30
adapted to tailor the output format into one of two output modes, tristate and JEDEC. The JEDEC mode of operation corresponds to a mode of error detection defined by Joint Electron Device Engineering Council (JEDEC) standards. The output circuit
30
includes multiplexers
32
,
33
that are enabled during the tristate mode of operation, and multiplexers
34
,
35
that are enabled during the JEDEC mode of operation. Mutually exclusive logic signals, TRI and JED on lines
36
,
37
, respectively, determine the particular multiplexers
32
,
33
,
34
,
35
that are enabled.
To operate in the tristate output mode, the TRI signal is held at a logically high state to enable the multiplexers
32
,
33
. The JED signal is held at a logically low state to disable the multiplexers
34
,
35
. The multiplexer
32
receives the output of the first portion
14
of the compression circuit
10
, where the first portion
14
outputs a logic “0” to indicate a pass condition and a logic “1” to indicate a fail condition. The output of the multiplexer
32
is coupled to the gate input of a p-type transistor
38
. The transistor
38
is connected between a voltage source
39
(e.g., about 2.2V) and an output terminal
40
. When the first portion
14
of the compression circuit
10
indicates a pass condition (i.e., logic “0”), the transistor
38
is enabled and the voltage at the output terminal
40
is pulled to a logically high state by the voltage source
39
. During a fail condition (i.e., logic “1”) the transistor
38
is disabled, disconnecting the power source
39
from the output terminal
40
.
The multiplexer
33
receives the output of the second portion
16
of the compression circuit
10
, where the second portion
16
outputs a logic “1” to indicate a pass condition and a logic “0” to indicate a fail condition. The output of the multiplexer
33
is coupled to the gate input of an n-type transistor
42
. The transistor
42
is connected between the output terminal
40
and ground. When the second portion
16
of the compression circuit
10
indicates a pass condition (i.e., logic “1”), the transistor
42
is enabled and the voltage at the output terminal
40
is pulled to a logically low state. During a fail condition (i.e., logic “0”) the transistor
42
is disabled, disconnecting the output terminal
40
from ground.
The portion
14
,
16
of the compression circuit
10
that indicates a passing condition will control the voltage on the output terminal
40
. The voltage on the output terminal
40
is read to determine the success or failure of the test. The value on the output terminal
40
of the compression circuit
10
matches the actual value that was written to the cells during the test. For example, if all logic “1” values were successfully read from the memory device, the first portion
14
would pass and the second portion
16
would fail. The compression circuit
10
would output a logic “1” to indicate the successful test. Conversely, if all logic “0” values were successfully read from the memory device, the second portion
16
would pass and the first portion
14
would fail. The compression circuit
10
would output a logic “0” to indicate the successful test. If both portions
14
,
16
indicate a fail condition, the output terminal
40
is tristated and has a voltage of about 1.1V.
To operate in the JEDEC output mode, the JED signal is held at a logically high state to enable the multiplexers
34
,
35
, and the TRI signal is held at a logically low state to disable the multiplexers
32
,
33
. The outputs of the first and second portions
14
,
16
of the compression circuit
10
are received by an XOR gate
44
. In the circuit of
FIG. 1
, the XOR gate
44
is a two input gate, however, the actual transistors (not shown) that define the XOR gate
44
require the both the input signal and its compliment to operate. Accordingly, the output of the inverter
22
, its compliment (i.e., the input to the inverter
22
), the input of the inverter
28
, and its compliment (i.e., the output of the inverter
28
) are provided to the XOR gate
44
. Unlike the example described above for the tristate mode, the input of the inverter
28
indicates pass or fail as opposed to the output of the inverter
28
. Accordingly, a pass condition is denoted by a logic “0” at the input of the inverter
28
.
The output of the XOR gate
44
is inverted by an inverter
46
. The output of the inverter
46
is provided to the multiplexers
34
,
35
. If only one of the first and second portions
14
,
16
of the compression circuit
10
indicates a pass condition (i.e., one portion
14
,
16
has a logic “0” and the other has a logic “1”), the XOR gate
44
outputs a logic “1”, which is inverted by the inverter
46
. The resulting logic “0” is provided to the multiplexers
34
,
35
, thus enabling the transistor
38
and pulling the voltage at the output terminal
40
to a logically high state. Conversely, if both the first and second portion
14
,
16
pass or both fail, the XOR gate
44
outputs a logic “0”, which is inverted by the inverter
46
. The resulting logic “1” is provided to the multiplexers
34
,
35
, thus enabling the transistor
42
and pulling the voltage at the ou

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