Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-07-10
2007-07-10
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000
Reexamination Certificate
active
10930882
ABSTRACT:
In one embodiment, the present invention includes a cache memory having a plurality of cache lines to store data, in which at least some of the cache lines are adapted to store data in a compressed state. The cache memory also may include a first tag corresponding to each of the cache lines to indicate whether data in the corresponding cache line is compressible.
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Adl-Tabatabai Ali-Reza
Ghuloum Anwar
Lueh Guei-Yuan
Peng Jinzhan
Ying Zhiwei
Dudek Edward J
Intel Corporation
Kim Matthew
Trop Pruner & Hu P.C.
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