Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-07-24
1999-02-23
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711126, G06F 1208
Patent
active
058754547
ABSTRACT:
A system and related architecture for providing random access cache storage between a processor accessing data at high speed and in small block units and a mass storage medium holding data in large transfer units. Lossless data compression is applied to large transfer units of data before storage in a DRAM. Cache address space is assigned in allocation units which are assigned without a prespecified pattern within the DRAM but linked through chains. The chain lengths are adjusted to match the compressibility characteristics of transfer units and include resources for scavenging residuals. Logical blocks materially smaller than the transfer units are accessed and decompressed during readout from the DRAM. The system architecture provides resources for accessing the individual logical blocks through an index. The invention is particularly suited for a disk drive cache system having a small cache DRAM in conjunction with a magnetic or optical disk mass storage system reading highly compressible data.
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Craft David John
Greenberg Richard
International Business Machiness Corporation
Lee Felix B.
Salys Casimer K.
Swann Tod R.
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