Compound semiconductor field effect transistor and method...

Details Compound semiconductor field effect transistor and method... Compound semiconductor field effect transistor and method...

2000-05-26

2002-08-06

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S200000, C257S279000, C257S609000, C257S631000, C257S743000, C438S602000, C438S604000

Reexamination Certificate

active

06429471

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to compound semiconductor field effect transistors and, more particularly, to compound semiconductor field effect transistors suitable for high output power.
Field effect transistors using compound semiconductor, hereinafter referred to as compound FETs, have been used as a high frequency transistor in the field of mobile communication. Generally, the compound FET is implemented in the form of MESFET (Metal Semiconductor FET) or in the form of MISFET (Metal Semiconductor Insulator FET). This is because, unlike the case of using silicon, it is impossible to prepare a MOSFET since it is extremely difficult to form, on a surface of a compound semiconductor substrate, an oxide film capable of providing a semiconductor-insulator junction which is stable and whose surface order is low. Accordingly, whereas a silicon FET is formed on a conductive substrate, a MESFET or MISFET is formed by the use of an insulating compound semiconductor substrate or semi-insulating compound semiconductor substrate. Hereinafter, throughout the specification, by the term “semi-insulating” is meant at lest “semi-insulation” and the term includes also “insulation”.
The way of fabricating a compound FET is divided, in terms of how its semiconductor layer is formed, roughly into two types, namely a method which employs ion implantation and another which employs epitaxial growth. The epitaxial growth process has several advantages over the ion implantation process. One of the advantage is that it is possible to form semiconductor layers high in impurity concentration and thin in film thickness, thereby making it possible to provide high-gain compound FETs. Another advantage is that, in MISFET, such a structure that the gate is not brought into direct contact with an active (operational) layer can be formed by using a high-purity intrinsic compound semiconductor layer (e.g., a non-dope aluminum gallium arsenic (i-AlGaAs)) as a gate contact layer, thereby allowing the realization of FETs capable of high current drive while at the same time securing a high breakdown voltage with no sacrifice in breakdown voltage, which is difficult for the ion implantation process to achieve. Owing to these advantages over the ion implantation process, there has been more need for epitaxially-grown compound FETs capable of serving as a high-frequency high output power FET for use in, for example, portable telephone power amplifiers.
Based on the phenomenon that the width of a depletion layer that is formed in an active layer (which is also called an electron transit layer or a channel) formed over a semi-insulating compound semiconductor substrate varies according to the level of the gate voltage, the compound FET controls a source-drain current. However, since the active layer is formed on the semi-insulating substrate, this will give rise to a problem of causing the compound FET to vary in its current-voltage characteristic (the I-V characteristic) when a high electric field is internally created.
The cause of such FET I-V characteristic variation will be discussed below.
Upon creation of a high electric field in the inside of a compound FET, electrons are accelerated by the high electric field to come to have high energy. When such a high energy electron collides with the lattice, this creates an electron-hole pair (an ion), which phenomenon is called “impact ionization”. Typically, the active layer is an n-type compound semiconductor layer and, of the created electron-hole pair, the electron merges with a carrier of the active layer and then flows to the high potential side, that is, towards the drain. On the other hand, the created holes are injected into the substrate. As a result, the potential of the substrate increases and the injected holes are accumulated around under a gate of the substrate. Due to the influence of the holes, the width of a depletion layer in the active layer varies, and there occurs a change in the FET current-voltage characteristic.
FIGS. 15A and 15B
each show a band structure for a gate electrode
76
, an active layer (n-GaAs)
74
, and a semi-insulating substrate (i-GaAs)
72
in an n-type gallium arsenic (GaAs)-including MESFET.
FIG. 15A
shows a state immediately after an electron-hole pair has been created by impact ionization.
FIG. 15B
shows an approximately stable state after a definite period of time has elapsed since the electron-hole pair creation. As can be seen from
FIG. 15A
, of the electron-hole pairs created in the active layer
74
, the holes are liable to accumulate under the gate electrode along the potential surface of VB (valence band) or enter into the substrate
72
. Upon injection of the holes into the substrate
72
, the electric potential of the semi-insulating substrate
72
, which is in agreement with a Fermi level (E
F
) in
FIG. 15A
, increases by an amount of &Dgr;Vsub as shown in FIG.
15
B. As a result, the width of the depletion layer
75
that is formed between the active layer
74
and the substrate
72
becomes narrower than that of FIG.
15
A. Such a reduction in the depletion layer width caused by the holes being injected into the semi-insulating substrate
72
is similar to the phenomenon that the depletion layer width is reduced when there is an increase in the p-type impurity concentration in a P/N contact. A reduction in the width of a depletion layer below the gate electrode
76
means that the region that contributes to conduction within the active layer
74
will increase, so that there is an increase in the drain current even when both the gate voltage and the drain voltage are constant. Such a phenomenon appears as a kink (bent)
78
in the I-V curve, as shown in FIG.
16
.
Referring now to
FIGS. 16A and 16B
, there are graphically shown I-V curves for different gate voltages of the compound FET, wherein the abscissa indicates the drain voltage and the ordinate the drain current. Whereas
FIG. 16A
shows an ideal I-V curve,
FIG. 16B
shows a conventional FET I-V curve. As described above, if the depletion layer width is narrowed by holes and the region that contributes to conduction within the active layer
74
increases, this results in a sudden increase in the drain current. As a result, the I-V curve bends, in other words the kink
78
is produced. Accordingly, in the vicinity of such a kink in the I-V curve, it is impossible to obtain a desired drain current even when performing control of the gate and drain voltages. Moreover, as the drain current varies, generally the FET optimum matching impedance varies considerably. This means that a FET that suffers a kink cannot be served as a high frequency power amplification FET the important requirement for which is impedance matching.
In order to obtain high-frequency high output power FETs, the realization of a high breakdown voltage (i.e., a high gate breakdown voltage) has been demanded, together with the controlling of the creation of kinks in the I-V curve.
An example of the kink creation control in MESFET is disclosed by M. Nagaoka et. al., in their paper entitled “High efficiency, low adjacent channel leakage 2-V operation GaAs power MESFET amplifier for 1.9 GHz digital cordless phone system”, IEEE MTT-S Digest, pp.1323-1326, 1997. Referring to
FIG. 17
, there is schematically illustrated a MESFET
1200
disclosed in the document.
The MESFET
1200
has a semi-insulating substrate
82
formed of i-GaAs, an n-type active layer
86
formed by implantation of ions into the semi-insulating substrate
82
, and three different electrodes (i.e., a source electrode
87
, a drain electrode
88
, and a gate electrode
89
) which are formed on their respective regions over the n-type active layer
86
. The n-type active layer
86
has an n-type compound semiconductor layer
86
c
formed below the gate electrode
89
, an n-type compound semiconductor layer
86
b
formed adjacent to each side of the n-type compound semiconductor layer
86
c
, and an n
+
semiconductor layer
86
a
for the establishment of ohmic contact with each

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