Active solid-state devices (e.g. – transistors – solid-state diode – Including region containing crystal damage
Reexamination Certificate
1997-02-26
2002-07-16
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Including region containing crystal damage
C257S609000, C257S610000, C438S407000
Reexamination Certificate
active
06420775
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a compound semiconductor device such as an integrated circuit including a field effect transistor (FET), and more specifically, to a compound semiconductor device having improved resistance to a backgate effect from the surface of a substrate.
2. Description of the Related Art
A compound semiconductor typified by GaAs features higher electron mobility than that of Si and the development of compound semiconductor devices such as analog signal amplifier circuits having ultra-high-frequency elements such as an MES type field effect transistor, Schottky barrier diode or the like integrated thereon, logic gates, memories and the like is actively underway. However, for the implementation of these compound semiconductor devices, there are big problems to be solved such as a sidegate effect in which a potential difference between an element such as an FET on the front surface of a substrate and another element formed on the front surface of a substrate modulates the channel layer of that FET through the substrate and affects the element characteristics of the FET, for example, drain current. Another of such problems is a backgate effect which is caused by the potential difference between an element on the front surface of a substrate and an electrically grounded electrode on the back surface of the substrate.
FIG. 4
shows a differential amplifier circuit called “source coupled FET logic (SCFL)” which is often used in the digital or analog circuit of a compound semiconductor. This type of circuit is introduced on page 435 of “GaAs DEVICES AND CIRCUITS”, Plenum Press (Michael Shur, New York and London), for example. In
FIG. 4
, reference numeral
51
denotes a MESFET;
52
, a resistor;
53
, a diode;
54
, a positive power source terminal;
55
, a negative power source terminal;
56
, an input terminal; and
57
, an output terminal. This type of circuit employing a Si bipolar transistor in place of the FET is called “emitter coupled logic (ECL)”. Since both circuits operate at almost the same voltage and speed, they can be replaced with each other and selected according to the purpose of use and considering characteristics such as the steepness of the waveform of the circuit and power consumption, costs and the like.
To replace a Si bipolar device by a compound semiconductor device, it is necessary to match the shape of a circuit chip and the position of a bonding pad in order to use the same package. Generally speaking, since an ECL is grounded to a positive power source, a compound semiconductor device may be designed to be grounded not only to a negative power source but also to a positive power source in order to replace an Si bipolar device. That is, as shown in
FIG. 2
, the rear surface of an ordinary chip is bonded to a metal carrier
14
of a package which serves both for heat radiation and electrical grounding using a solder material
13
having a low melting point. It is possible that the carrier
14
is connected to either the positive power terminal
54
or the negative power terminal
55
of the SCFL shown in FIG.
4
. In either one of the grounding systems, the source of the MESFET
51
on the input side of the SCFL is at an intermediate potential and a sidegate effect or a backgate effect caused by the operation of the circuit becomes a problem to be solved.
In IEEE Electron Device Letters, Vol. EDL-4, No.4, pp. 102-103, “Self-Aligned Sub-micron Gate GaAs Integrated Circuits”, an attempt to improve such a sidegate effect in a compound semiconductor device by implanting ions such as protons H
+
, boron ions B
+
or oxygen ions O
+
to form a defective region between FET elements formed on a semi-insulating GaAs substrate is proposed . The principle that the sidegate effect is improved by this method is described in the Technical Report of IEICE (the Institute of Electronics Information and Communication Engineers), Vol.91, No.321, ED 91-119, pp.19-24, “GaAs Element Separation Mechanism by Defects Formed by Implantation of B
+
Ions”.
However, since a defective region is formed only on the front surface of the substrate in this FET structure, it has no effect when the potential of the rear surface of the substrate varies. Further, when the total area of adjacent electrodes on the front surface of the substrate, for causing a sidegate effect, is much larger than that of the FET concerned, the effect of the defect region is weakened, whereby the amount of a field generated through a deep portion of the substrate increases and a backgate effect appears, thereby causing fluctuations in the characteristics of the FET.
Several proposals for forming a layer having a deep level under an FET channel layer have been made to improve backgate voltage resistance of the substrate side.
FIG. 5
is a sectional view of a semiconductor device (to be referred to as “first conventional example” hereinafter) proposed in IEEE, Transactions on Electron Devices, Vol.37, No.1, 1990, pp.46-50, “Anomalies in MODFET's with a Low-Temperature Buffer”. In this conventional example, a low-temperature growth i-type GaAs layer
62
, a normal-temperature growth i-type GaAs layer
63
and an n-type GaAs layer
64
are grown on a semi-insulating GaAs substrate
61
sequentially and a source electrode
66
, a gate electrode
67
, a drain electrode
68
and a sidegate
69
are formed on the n-type GaAs layer
64
to separate these elements by an ion implanted defect layer
65
. The term “sidegate” as used herein defines an electrode adjacent to an affected FET (FET shown at the center of the figure) and having a sidegate effect on the FET and generally refers to the conductive region or electrode of an FET or diode.
The MBE growth of GaAs is generally carried out at around a temperature of 600° C. However, in this conventional example, part of a buffer layer (
62
) is formed at a growth temperature of 200 to 300° C. to generate defects (deep levels) in this layer with an excessive amount of arsenic (As).
As a second conventional example, as shown in
FIG. 6
, formation of a layer doped with deep level generating impurities by continuous epitaxial growth is proposed in Laid-open Japanese Patent Application (KOKAI) No. Hei 3-3336. In this conventional example, an i-type GaAs buffer layer
72
, a 400-nm-thick Cr doped GaAs layer
73
having a Cr concentration of about 5×10
16
cm
−3
as an impurity for generating a deep level, a p-type GaAs layer
74
and an n-type GaAs layer
75
are epitaxially grown sequentially on a semi-insulating GaAs substrate
71
, and a source electrode
76
, a gate electrode
77
and a drain electrode
78
are formed on the n-type GaAs layer
75
. Fe (iron), Ni (nickel) or oxygen may be used in place of Cr. An embodiment in which the Cr doped GaAs layer
73
is inserted between the semi-insulating GaAs substrate
71
and the i-type GaAs buffer layer
72
is shown in the document as well.
As a third conventional example, as shown in
FIG. 7
, the formation of an ion implanted defect layer
82
at a position deeper than an active layer in a semi-insulating GaAs substrate
81
is proposed in Laid-open Japanese Patent Application (KOKAI) No. Hei 4-49627. In this conventional example, after the ion implanted defect layer
82
is formed, silicon is selectively implanted to form an n-type GaAs layer
83
and a source electrode
84
, a gate electrode
85
and a drain electrode
86
are formed on the n-type GaAs layer
83
. Boron is selected as an impurity for forming the ion implanted defective layer
82
and implanted at 150 keV in an amount of 1×10
15
cm
−2
ions. Protons or oxygen ions may be implanted in place of boron ions.
As a fourth conventional example different from the above two, as shown in FIG,
8
, the formation of an insulating film
92
between a semi-insulating GaAs substrate
91
and a rear-surface electrode
93
is proposed in Laid-open Japanese Patent Application (KOKAI) No. Sho 63-48869. An n-type GaAs layer
96
is formed on the front s
NEC Corporation
Weiss Howard
Young & Thompson
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