Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Fluid growth from gaseous state combined with subsequent...
Reexamination Certificate
1998-05-22
2001-06-05
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Fluid growth from gaseous state combined with subsequent...
C117S104000
Reexamination Certificate
active
06242327
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a high-speed compound semiconductor device having a reduced source resistance.
Compound field effect semiconductor devices such as a MESFET or HEMT have a structure in which a gate electrode is provided on a semiconductor substrate that provides a channel layer, and a pair of ohmic electrodes are formed at both lateral sides of the gate electrode as source and drain electrodes. Thereby, the part of the substrate that contacts the source electrode or drain electrode forms a source region or a drain region. In such compound field effect semiconductor devices, it is desired to reduce the resistance of the source region or drain region as much as possible for improving the operational speed of the semiconductor device.
Thus, there has been a proposal to form an ion-implanted region in the substrate in correspondence to the source region or drain region so as to reduce the source resistance or drain resistance of the semiconductor device similarly to the case of a conventional MOS transistor constructed on a Si substrate.
Generally, formation of such an ion-implanted region is achieved by an ion implantation process, wherein an ion implantation process generally includes a thermal annealing process conducted after the step of introducing accelerated ions, as is well known in the art.
In the case of a III-V compound semiconductor device, however, there is a tendency that the group V element such as As or P causes a dissociation during such an annealing process, and thus, it has been necessary to conduct the annealing process in an atmosphere of the foregoing group V element or in a state in which the surface of the compound semiconductor substrate is covered by an insulation film, for avoiding such a dissociation of the group V element.
FIG. 1
shows an example of a conventional annealing process as applied to a GaAs HFET (heterostructure FET).
Referring to
FIG. 1
, the GaAs HFET is constructed on a semi-insulating GaAs substrate
11
and includes a first compound semiconductor layer
12
A of an undoped GaAs or a low-resistance GaAs doped to the p
−
-type on the foregoing semi-insulating GaAs substrate
11
. Further, a second compound semiconductor layer
12
B is formed on the first compound semiconductor layer
12
A as a channel layer of the semiconductor device, wherein the second compound semiconductor layer
12
B may be formed of undoped or n-type GaAs, InGaAs or InGaAsP. It should be noted that the first compound semiconductor layer
12
A functions as a carrier blocking barrier preventing a leakage of carriers from the channel layer
12
B to the substrate
11
. Such a leakage of carriers tends to occur in extremely miniaturized devices in which a short channel effect appears conspicuously.
On the channel layer
12
B, a gate electrode
13
of WSi is provided, and the channel layer
12
B as well as a part of the carrier blocking layer
12
A underneath the channel layer
12
B are subjected to an ion implantation process of an n-type dopant such as Si
+
at both lateral sides of the WSi gate electrode
13
while using the gate electrode
13
as a self-aligned mask. By applying an annealing process to the structure thus obtained, a source region
12
C and a drain region
12
D both of the n
+
-type are formed in the channel layer
12
B at both lateral sizes of the gate electrode
13
.
When applying an annealing process in such a structure, it is generally practiced to provide an insulation film
14
of SiO
2
, SiN, AlN or SiON on the substrate
11
for preventing the dissociation of the group V element from the III-V compound semiconductor crystal forming the first or second compound semiconductor layers. Thus, the insulation film
14
is provided so as to cover the channel layer
12
B as well as the gate electrode
13
thereon.
After the structure of
FIG. 1
is formed, the insulation film
14
is removed selectively, and source and drain electrodes (not illustrated) are formed on the source region
12
C and the drain region
12
D.
In the foregoing process of
FIG. 1
, the problem of dissociation occurring in the channel layer
12
B, which is essential for the operation of the semiconductor device, is successfully eliminated by conducting the annealing process in the state that the insulation film
14
is provided.
On the other hand, the structure of
FIG. 1
includes a triple point A in the structure as indicated, wherein it should be noted that the triple point A is a point in which all of the channel layer
12
B, the insulation film
14
and the gate electrode
13
make a contact with each other. Because of the difference in the thermal expansion coefficient, the triple point A tends to accumulate a severe thermal stress, while such a thermal stress in the triple point A tends to induce a stress and hence crystal defects inside the channel layer
12
B, particularly in the vicinity of the gate electrode
13
. Thereby, the operational performance of the semiconductor device is substantially deteriorated.
Further, the conventional device of
FIG. 1
suffers from the problem of difficulty in controlling the profile of the impurity element at the time of the annealing process.
Meanwhile, there is proposed a process of forming a low-resistance source region or a low-resistance drain region by growing a conductive compound semiconductor layer on a compound semiconductor substrate selectively as source and drain regions.
FIGS. 2A-2C
show a conventional process of forming a compound field effect semiconductor device
21
carrying the selectively grown source and drain regions.
Referring to
FIG. 2A
, the semiconductor device is constructed on a semi-insulating GaAs substrate
22
and a channel region
22
A of the n-type is formed on the semi-insulating GaAs substrate
22
. Further, an insulation layer
23
of SiON is formed on the substrate
22
, and the insulation layer
23
is formed with openings
23
A and
23
B exposing the surface of the substrate
22
in correspondence to the source region and the drain region of the semiconductor device to be formed.
Next, in the step of
FIG. 2B
, an MOVPE process is conducted by using TMGa (trimethylgallium) or TEGa (triethylgallium) and arsine (AsH
3
) respectively as a gaseous source of Ga and As, with silane (SiH
4
) added thereto as a gaseous source of dopant. As a result of the MOVPE process, a source region
24
A and a drain region
24
B of n
+
-type GaAs are grown selectively on the substrate
22
in correspondence to the foregoing openings
23
A and
23
B. Further, a Schottky electrode
25
is formed in the step of
FIG. 2C
between the source region
4
A and the drain region
4
B.
FIG. 3
shows the construction of a MOVPE apparatus
30
used in the step of
FIGS. 2A-2C
, particularly in the step of
FIG. 2B
, for forming the source region
24
A and the drain region
24
B by the selective growth process.
Referring to
FIG. 3
, the MOVPE apparatus
30
includes a reaction chamber
31
in which a holder
31
B is provided in a rotatable manner by a motor
31
A, wherein the holder
31
B carries a susceptor
31
C and the susceptor
31
C supports thereon a wafer
31
D. Further, a heater
31
E is provided in the reaction chamber
31
in correspondence to each of the susceptors
31
C.
It should be noted that the MOVPE apparatus
30
further includes a carrier gas line
32
to which a carrier gas such as H
2
is supplied. Further, the MOVPE apparatus
30
includes gas cylinders
33
A and
33
B respectively holding an arsine gas and a silane gas as an As source and a dopant, wherein arsine in the cylinder
33
A is supplied to the reaction chamber
31
via a valve
33
a
and a line
34
, together with the carrier gas supplied to the foregoing line
32
. Similarly, silane in the cylinder
33
B is supplied to the reaction chamber
31
together with the carrier gas through the line
32
, via a valve
33
b
and the line
34
cooperating with the gas cylinder
33
B.
In addition, the MOVPE apparatus
30
of
FIG. 3
Tanaka Hitoshi
Wada Jun
Yokoyama Mitsunori
Armstrong, Westerman Hattori, McLeland & Naughton
Chaudhuri Olik
Fujitsu Limited
Willie Douglas A.
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