Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
1999-07-21
2001-03-13
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C257S192000
Reexamination Certificate
active
06200838
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a compound semiconductor device and a method of manufacturing the same and, more particularly, an FET manufacturing method utilizing a field effect transistor (referred simply to as an “FET” hereinafter) and an ion implantation process.
2. Description of the Prior Art
As typical devices as a transistor employing compound semiconductor, there are a GaAs MES FET (Metal Semiconductor FET), a HEMT (High Electron Mobility Transistor), etc. The GaAs MES FET has such features that a high frequency operation can be achieved with low noise, a high speed switching operation can be achieved, etc. Thus, the GaAs MES FET is suitable for various applications, e.g., a high frequency/high output amplifier, a high frequency/low noise amplifier, a high speed change-over switch, etc. At present, the GaAs MES FET has been broadly used as a gate array, an amplifier IC in the mobile communication, a high speed optical communication IC, etc. Also, with the progress of information communication technology in recent years, a higher operational speed of the device is now requested.
The GaAs semi-insulating substrate is employed in the GaAs MES FET, and GaAs is a compound semiconductor consisting of a group III element and a group V element. A device using such compound semiconductor is called a compound semiconductor device. Since Gals has a high electron mobility and a high saturation drift velocity, it is fitted for a high speed/high frequency device. More particularly, the electron mobility in a pure GaAs is higher about five times than silicon (Si), and a peak velocity of the saturation drift velocity of the pure GaAs is higher about twice than the saturation velocity of Si. In addition, since the pure GaAs has the high mobility, an electric field required for the peak velocity is small rather than Si. Further, since GaAs can be formed as a crystal with higher resistance rather than Si, such GaAs is called a semi-insulating crystal. Therefore, if a single device or an integrated circuit is fabricated by using a semi-insulating substrate, a parasitic capacitance can be reduced generally and device isolation can be facilitated.
As with GaAs MES FET manufacturing method, the self-alignment FET employs the gate electrode made of WSi, or the like, whose gate characteristic is not deteriorated even when the high temperature annealing process is applied to the gate electrode, as a mask for n
+
ion-implantation. Such self-alignment FET has a very small source resistance Rs because an n
+
layer is formed in close vicinity of the gate, and the manufacturing steps are relatively simple because such self-alignment FET is formed as a simple planar structure without a recess structure, so that such self-alignment FET has been broadly used.
An operation speed of the MES FET is decided by a cut-off frequency f
T
which is in inverse proportion to the gate length Lg. Therefore, in order to accelerate the operation speed, it is an effective means to reduce the gate length Lg. However, in reducing the gate length Lg, sometimes a phenomenon which is called a short channel effect such as increase in a drain conductance or increase in a well up current occurs to thus deteriorate device characteristics.
Following points can be pointed out as causes of the short channel effect.
(1) The channel thickness tch must be reduced to mate with reduction of the gate length Lg and also impurity concentration of the channel region must be increased such that an aspect ratio of gate length/channel thickness (Lg/tch) is not so reduced. However, this aspect ratio is not set in the appropriate range. The gate length is a length of the gate electrode in a direction from a source region to a drain source region.
(2) The potential of a depletion layer immediately below the gate electrode extends downward with the reduction of the gate length Lg, so that thermionic emission into the semi-insulating substrate becomes prominent.
(3) The current which flows between opposed n
+
regions, i.e., a highly doped layer below the source electrode and a highly doped layer below the drain electrode, via the semi-insulating substrate is increased.
Among these causes of the short channel, it is evident that the cause (1), i.e., the aspect ratio (Lg/tch) is not set in the appropriate range, can be improved by executing the ion-implantation into the n-type channel region at the low energy and the high dosage.
In order to prevent the thermionic emission into the semi-insulating substrate set forth in the cause (2) and the increase in the current flowing between the opposed n
+
regions set forth in the cause (3), the structure which is known as the “buried p type region” is effective. In the buried p type region structure, the buried p type region is formed in the semi-insulating substrate side which contacts the channel region and the n
+
region to form pn junction and thus depletion layers are formed on interfaces between the channel region and the n
+
region and the semi-insulating substrate to prevent the leakage current.
FIGS. 1A
to
1
C are views showing the typical buried p type region structure in the FET as the compound semiconductor device in the prior art.
FIG. 1A
is a sectional view showing the compound semiconductor device employing the buried p type region structure,
FIG. 1B
is a plan view (top view) showing the buried p type region structure in
FIG. 1A
, and
FIG. 1C
is a sectional view showing an issue of the compound semiconductor device in the prior art, i.e., leakage current paths between elements. In the compound semiconductor device employing the buried p region structure shown in
FIGS. 1A
to
1
C, a p-type impurity region
20
is formed on a surface of a semi-insulating substrate
10
by ion implantation using photoresist (not shown) as a mask, and then an n-type active region (channel region)
40
is formed by another ion implantation using the same photoresist (not shown) as a mask. Then, a gate electrode
50
is formed on the channel region
40
, then openings (not shown) on the semi-insulating substrate
1
are formed in an SiO
2
film (not shown) and a photoresist film (not shown) on the basis of the gate electrode
50
as an alignment mark, and then a high concentration n-type impurity region (source region)
60
-
1
and a high concentration n-type impurity region (drain region)
60
-
2
are formed by ion implantation on both sides of the gate electrode
50
via the openings in a self-alignment manner. These regions are then activated by the annealing process, and then a source electrode
80
-
1
and a drain electrode
80
-
2
are formed.
Next, conception of the buried p structure will be explained in brief with reference to
FIGS. 2A
to
2
C hereunder. As shown in
FIG. 2A
, the buried p type structure has a p-type impurity region
20
which is buried below the n-type active region
40
, the high concentration n-type impurity region
60
-
1
and the high concentration n-type impurity region
60
-
2
.
FIG. 2B
is a view showing an ion implantation energy in the buried p structure at a depth x from the surface of the substrate
1
which corresponds to positions of the n-type active region
40
and the p-type impurity region
20
in FIG.
2
A. In
FIG. 2B
, the n-type and p-type impurities are overlapped on a boundary portion between the n-type active region
40
and the p-type impurity region
20
(shaded area). Carriers are canceled in this overlapping area and thus, as shown in
FIG. 2C
, n-type implantation carriers remains sharply in the n-type active region
40
, whereby the thin channel can be formed. The pn junction below the thin channel is formed as a depletion region.
However, it has already been found that, when the device shown in
FIGS. 1A
to
1
C is manufactured actually by way of trial, the leakage current generated by the n-type conduction (electron conduction)
11
between fringes of the high concentration n-type impurity regions
60
-
1
,
60
-
2
, as shown in
FIG. 1C
, is increas
Inoue Kazutaka
Matsuda Hajime
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Quantum Devices Limited
Lee Calvin
Smith Matthew
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