Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-24
2004-04-27
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S240000, C257S241000, C257S243000, C257S266000, C257S280000, C257S401000, C257S402000, C257S472000, C257S631000, C257S459000, C436S167000, C436S169000, C436S169000, C436S534000, C436S534000
Reexamination Certificate
active
06727559
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The invention relates to a compound semiconductor device employed in a device operating at high frequency, specifically to a compound semiconductor device with reduced size and improved high frequency characteristics.
2. Description of the Related Art:
The demand for high frequency devices has been rapidly increasing due to the expanding market for portable telephones and digital satellite communication equipment. Many of such devices include field effect transistors (referred to FET, hereinafter) employing a gallium arsenide (referred to GaAs, hereinafter) substrate because of its excellent high frequency characteristics. A typical device in this field is a local oscillation FET.
FIG. 1
is a cross-sectional view of a conventional GaAs FET. The GaAs substrate
151
is initially undoped, and has an n type channel region (or a channel layer)
152
formed by doping with n type dopants beneath its surface. A gate electrode
153
is placed on the surface of the channel region
152
, forming a Schottky contact, and a source electrode
154
and a drain electrode
155
are placed on both sides of the gate electrode
153
, forming ohmic contacts to the surface of the channel region
152
. In this configuration, a voltage applied to the gate electrode
153
creates a depletion layer within the channel region
152
beneath the gate electrode
153
and, thus, controls the channel current between the source electrode
154
and the drain electrode
155
.
FIG. 2
shows a conventional local oscillation FET employing a GaAs substrate. A channel region
62
is formed on a GaAs substrate and has therein a source region and a drain region. A first layer made of ohmic metal layer (AuGe/Ni/Au)
60
is formed on the source and drain regions to provide the source electrode and the drain electrode of the FET. A second layer made of a gate metal layer (Ti/Al)
70
is formed simultaneously when a gate electrode of the FET is formed. The second layer is denoted by the broken line in
FIG. 2. A
third layer made of a pad metal layer (Ti/Pt/Au)
80
provides connecting pads
81
,
82
,
83
for the drain electrode, the source electrode and the gate electrode. The source connecting pad
82
prevents signal leakage between the drain connecting pad
81
and the gate connecting pad
83
, occupying a space between the two connecting pads
81
,
83
. Broken circles in
FIG. 2
denote wire bonding positions on the connecting pads. Four bonding wires are bonded to the source connecting pad
82
, and two bonding wires are bonded to each of the drain connecting pad
81
and the gate connecting pad
83
. All the bonding wires are bonded to the respective connecting pads by applying pressure and heat to the contact region. The source connecting
82
is connected to a ground terminal GND via a capacitor C.
In
FIG. 2
, the channel region
62
is the rectangle denoted by the unevenly broken line. The two strips of the pad metal layer
80
extending from the drain connecting pad
81
are the drain electrode. The drain electrode made of the ohmic metal layer
60
is placed underneath the drain electrode made of the pad metal layer. The comb like structure with three teeth extending from the topside of the device is the source electrode made of the pad metal layer
80
. The source electrode made of the ohmic metal layer
60
is placed underneath the source electrode made of the pad metal layer
80
. The gate electrode is placed between the strips of the drain electrode and the teeth of the source electrode. The gate electrode is made of the gate metal layer and formed on the channel layer
62
. In this configuration, the gate width Wg of the FET is defined as the summation of the lengths of the gate electrode within the channel layer
62
of the FET. Accordingly, in this FET, the total length of the four portions of the gate electrode between the strips and the teeth within the channel region
62
provides the gate width Wg. The FET of
FIG. 2
has a gate width of 400 &mgr;m.
The pad metal layer
80
and the gate metal layer
70
do not intersect. In other words, this FET does not have a multi layer wiring structure. This is an important feature to avoid deterioration of high frequency characteristics of the GaAs FET due to parasitic capacitance. When the pad metal layer
80
and the gate metal layer
70
intersect each other, an insulating layer such as nitride film needs to be placed between the two layers. Such a design creates parasitic capacitance and induces leakage of the signals.
Thus, the conventional local oscillation FET is typically as large as 0.44×0.39 mm
2
because of the design constraint on the use of single layer wiring and the connecting pad alignment. However, size reduction of local oscillation FETs is required to reduce the cost of such devices.
SUMMARY OF THE INVENTION
The invention provides a compound semiconductor device including a compound semiconductor substrate having a substantially rectangular shape and a channel region formed on the surface of the substrate. A drain electrode, a gate electrode and a source electrode are each formed on the channel region. A drain connecting pad, a gate connecting pad and a source connecting pad are each connected to the respective electrodes. The drain connecting pad and the gate connecting pad are disposed substantially at respective corners of a first diagonal of the substrate and the source connecting pad is disposed substantially at a corner of a second diagonal of the substrate. The other corner of the second diagonal is not occupied by any other connecting pad. In this configuration, the first and second diagonals define the surface of the substrate on which the channel region is formed.
The invention also provides a compound semiconductor device including a compound semiconductor substrate having a substantially rectangular shape and a channel region formed on a surface of the substrate. A drain electrode, a gate electrode and a source electrode are each formed on the channel region. A drain connecting pad and a gate connecting pad are each connected to the respective electrodes. A first source connecting pad and a second source connecting pad are each connected to the source electrode. The drain connecting pad and the gate connecting pad are disposed substantially at respective corners of a first diagonal of the substrate and the first and second source connecting pads are disposed substantially at respective corners of a second diagonal of the substrate. In this configuration, the first and second diagonals define the surface of the substrate on which the channel region is formed. The angle made by the first and second diagonals of the substrate is between 30 and 60 degree. The gate electrode is substantially disposed in the direction of the first diagonal of the substrate.
The invention further provides a compound semiconductor device including a compound semiconductor substrate and a channel region formed on a surface of the substrate. A drain electrode, a gate electrode and a source electrode are each formed on the channel region. The drain, gate and source electrodes form a field effect transistor. A drain connecting pad and a gate connecting pad are each connected to the respective electrodes. A first source connecting pad and a second source connecting pad are each connected to the source electrode. The drain connecting pad and the gate connecting pad are disposed approximately symmetric to each other with respect to the channel region as the center of symmetry and the first and second source connecting pads are disposed approximately symmetric to each other with respect to the channel region as the center of symmetry. The gate electrode is disposed in the direction connecting the drain connecting pad and the gate connecting pad.
REFERENCES:
patent: 4737837 (1988-04-01), Lee
patent: 5148244 (1992-09-01), Iwasaki
patent: 5920083 (1999-07-01), Bae
patent: 6573529 (2003-06-01), Asano et al.
patent: 6597043 (2003-07-01), Naem
patent: 6627956 (2003-09-01), Asano et al.
Asano Tetsuro
Hirata Koichi
Sakakibara Mikito
Uekawa Masahiro
Morrison & Foerster / LLP
Ortiz Edgardo
Sanyo Electric Co,. Ltd.
Thomas Tom
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