Compound, high-K, gate and capacitor insulator layer

Details Compound, high-K, gate and capacitor insulator layer Compound, high-K, gate and capacitor insulator layer

1997-12-22

2003-04-15

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000, C257S310000, C257S311000, C257S312000, C257S313000, C257S314000

Reexamination Certificate

active

06548854

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits in general and, more particularly, to gate/capacitor dielectrics having a high dielectric constant (high K).
2. Description of the Prior Art
As feature sizes on integrated circuits gets smaller, the amount of capacitance for a given circuit element decreases, such as with a memory storage capacitor, and operating voltages are decreased.
For a transistor to operate reliably at lower voltages, the threshold voltage of the transistor is correspondingly lowered. One approach to lower the threshold voltage is to thin the insulating layer (usually a single layer of silicon dioxide) separating the transistor gate from the transistor channel. But at very thin insulating thicknesses (e.g., an oxide layer thickness of less than 3.5 nm), the oxide layer suffers from pinholes and leakage may be too large. Further, if the oxide layer is less than 2.5 nm, tunneling of electrons from the transistor channel may occur, degrading transistor performance. Alternatively, the gate may be effectively “moved” closer to the channel by incorporating a high dielectric constant (k) material as the gate insulator between the gate and the transistor channel. However, this approach with high-k materials (such as ferroelectric dielectrics) has not been entirely satisfactory because of defects within the dielectric and also at the silicon/dielectric interface, due for example by lattice mismatch, causing excessive gate to substrate leakage.
The reduced feature size and lower operating voltage is of special concern with dynamic memories where capacitors are used to store information. As more memory cells are added to a given memory array and feature sizes are decreased so that the extra cells can be added within a reasonable chip size, the size of the storage capacitors are correspondingly decreased. With lower capacitance of the storage capacitors and reduced voltage on the capacitors, the memory may become more error prone. To compensate for the reduction in capacitor size and still maintain capacitance, two approaches can be used singly or in combination: dielectric thinning and increasing the dielectric constant. But the same problems with both approaches discussed above apply here as well.
From a practical point of view, the use of high-k materials may be the most desirable choice to solve the above problems at feature sizes of 0.35 &mgr;m and below if the leakage/defects problems can be satisfactorily solved.
Therefore, there exists a need for incorporating high dielectric materials into integrated circuit designs with reduced defect and leakage problems of the heretofore approaches of device fabrication incorporating high dielectric constant materials.
SUMMARY OF THE INVENTION
This and other aspects of the invention may be obtained generally with an integrated circuit having an oxidizable layer having a surface, such as a silicon substrate or a polysilicon layer, having: a grown oxide layer on the oxidizable surface, a high-k dielectric layer on the grown oxide layer, and a deposited oxide layer on the high-k dielectric layer. Preferably, the grown oxide layer is grown from the substrate or polysilicon layer.


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