Compound domino logic circuit having output noise elimination

Details Compound domino logic circuit having output noise elimination Compound domino logic circuit having output noise elimination

1998-09-28

2001-01-09

Santamauro, Jon (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S028000, C326S121000

Reexamination Certificate

active

06172529

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to semiconductor circuits in general, and in particular to domino logic circuits. Still more particularly, the present invention relates to a compound domino logic circuit having output noise elimination.
2. Description of the Prior Art
A domino logic circuit simplifies digital logic by connecting a number of transistors together in series to implement digital combination logic. For example, a domino logic circuit implements a logic AND function by cascading a p-channel transistor with several n-channel input transistors in series between a power supply and ground. During operation, the p-channel transistor is clocked to precharge an output node of the circuit to a predetermined logic state. Depending on the logic state at the inputs of the n-channel input transistors, the output node either remains at its precharged state or is pulled low through the series of n-channel input transistors connected to ground.
It is quite common for logic gates, such as AND, OR, and their combinations, in certain high performance logic control circuits to have a large number of inputs. However, due to current technology limitations, it is impractical to stack more than four input transistors in a simple domino logic circuit configuration for supporting a large number of inputs; hence typically, a compound domino logic circuit structure having a large fan-in is utilized instead. Due to the size and the stacked configuration of the p-channel transistors at the output of a compound domino logic circuit, a charge sharing problem may occur at the nodes between the p-channel transistors. Consequently, it is desirable to provide a solution to the charge sharing problem in a compound domino logic circuit without adding noise to the output.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a compound domino logic circuit includes at least two trees of logic devices arranged in parallel, with each tree having a precharge transistor connected to a power supply, and one or more input transistors coupled between the precharge transistor and ground. The precharge transistor receives a clock input while each of the one or more input transistors receives a signal input. The compound domino logic circuit also includes a logic gate coupled to the precharge transistor to produce a signal output. The logic gate includes at least two transistors connected in series. Further, an adjustment transistor is coupled to a node between the two transistors to ground.
All features and advantages of the present invention will become apparent in the following detailed written description.


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