Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
2002-05-08
2004-03-09
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S503000, C438S507000, C438S931000
Reexamination Certificate
active
06703288
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a compound single crystal substrate employed as a substrate in semiconductor devices such as power semiconductor devices, light-emitting devices, and integrated circuits; a method of manufacturing this compound single crystal substrate; a laminate employing this compound single crystal substrate; and a method of manufacturing the laminate. In particular, the present invention relates to a low-defect density compound single crystal substrate desirable from the aspects of improving yield in the course of manufacturing semiconductor devices and the characteristics thereof; a method of manufacturing the same; and a method of employing the same.
BACKGROUND OF THE INVENTION
Conventionally, the substrates employed in semiconductor devices are in the form of ingots manufactured from compound semiconductor crystals, for example. Examples of widely employed methods of manufacturing ingots are the horizontal Bridgman method, Czochralski method, sublimation method, and zone melting method. The ingot obtained is generally cut into plates, externally processed, surface ground, and employed as a semiconductor wafer. Further, when manufacturing high-performance semiconductor devices, a film with few crystal defects and of low impurity concentration is epitaxially grown on a compound semiconductor substrate that has been processed from an ingot.
Further, it is sometimes difficult to manufacture a compound semiconductor as an ingot, and it is sometimes difficult to obtain large-area ingots for technical and cost reasons. In such cases, the means of forming an epitaxial layer of a desired compound semiconductor crystal on a relatively readily available semiconductor wafer in the form of an Si substrate or the like (heteroepitaxy) is sometimes employed.
However, in heteroepitaxy, there is mismatching of the lattice constants of the substrate crystal and the crystal grown on the layer above it. Thus, crystal defects resulting from this mismatch develop at the interface of the substrate crystal and the crystal grown over it. In particular, in compound semiconductor crystals, a greater variety of crystal defects develop than in crystals comprised of a single element, such as Planar defects (Anti-Phase boundaries) developing at boundaries between regions where the stacking order of constituent elements is reversed and defects (twins) developing where the crystal is partially rotated. Such crystal defects must be reduced to the extent possible in the manufacturing of semiconductor devices because, for example, they decrease breakdown voltage and increase leakage current. However, because primarily low-surface-energy planar defects grow, particularly during compound single crystal growth, they have been difficult to eliminate thus far.
Even in the case of homoepitaxially growing in which homogeneous crystals are grown, propagative planar defects propagate in the homoepitaxially grown layers of the substrate that is grown (for example, when the surface energy of the polar face exposed at the surface is low), making it difficult to obtain a homoepitaxially grown layer suitable as an underlayer in power semiconductor devices and the like.
For example, when silicon carbide (SiC) grows heteroepitaxially on an Si substrate, planar defects (anti-phase boundaries and twins) develop in an SiC film. One method of reducing such planar defects, comprising the step of providing a growth region on a grown substrate and a step of growing a single crystal silicon carbide crystal on the growth region to a thickness identical to or exceeding the natural thickness of the substrate along the orientation of the growth surface, has been proposed (Japanese Examined Patent Publication (KOKOKU) Heisei No. 6-41400). However, the two types of reverse phase regions in the SiC have a characteristic of expanding in a mutually perpendicular orientation as the thickness of the SiC film increases. Thus, it is impossible to effectively reduce the anti-phase boundary no matter how long heteroepitaxial growth is continued.
Another method of eliminating the mismatching of crystal lattices is to insert a new layer (buffer layer) having a lattice constant falling between those of the substrate and the layer grown over it. However, for example, when growing SiC on a Si substrate, no substance capable of serving as buffer layer is known. As a result, when SiC is grown directly on a Si substrate, there is 20 percent of mismatching between lattice constants. This is the main cause of planar defects in epitaxially grown SiC layers.
In the growth of gallium nitride (GaN), to eliminate high-density crystal defects generated between heterogeneous substrates, a layer temporarily blocking GaN growth is provided part way through the growth process. It has been proposed to reduce crystal defects growing in a vertical direction by utilizing lateral growth of GaN above an opening provided in part of the growth-blocking layer, wherein the GaN has selectively been grown through the opening (U.S. Pat. No. 6,051,849). However, this method requires the steps of forming a GaN growth-blocking layer and making a hole in it, which increases cost. Further, since crystal defects have the property of propagating unchanged into the GaN over the opening, crystal defects are not completely eliminated.
Accordingly, the objects of the present invention are to provide a compound semiconductor crystal substrate for epitaxial growth capable of reducing planar defects such as twins and anti-phase boundary occurring in epitaxially grown crystals without additional steps beyond epitaxial growth, and to provide a method of manufacturing the same.
A further object of the present invention is to provide a laminate employing the above-described compound semiconductor crystal substrate and a method of manufacturing the same.
SUMMARY OF THE INVENTION
The present invention relates to a compound single crystal substrate, a basal plane of which is a nonpolar face and said basal plane has a partial surface having polarity (hereinafter referred to a partial polar surface), characterized in that said partial polar surface is a polar portion with surface energy higher than said basal plane.
In this compound single crystal substrate, the compound is preferably a group IV—IV compound, group III-V compound, or group II-VI compound; the compound single crystal is preferably cubic, said basal plane is (001) face, and said partial polar surface is (111) face; the compound single crystal is preferably hexagonal, said basal plane is (1,1,−2,0) or (1,−1,0,0) face, and said partial polar surface is {0001} faces; the compound single crystal is preferably cubic silicon carbide, said basal plane is (001) face, and said partial polar surface is (111) Si-face; the compound single crystal is preferably cubic gallium nitride, said basal plane is (001) face, and said partial polar surface is (111) Ga-face; the compound single crystal is preferably hexagonal silicon carbide, said basal plane is (1,1,−2,0) or (1,−1,0,0) face and said partial polar surface is (0001) Si-face; and the compound single crystal is preferably hexagonal gallium nitride, said basal plane is (1,1,−2,0) or (1,−1,0,0) face, and said partial polar surface is (0001) Ga-face.
The present invention further relates to a method of manufacturing the above-mentioned compound single crystal substrate comprising the steps of: epitaxially growing a compound single crystal in the normal direction on a basal plane of a compound single crystal substrate wherein the basal plane is a nonpolar face and has a partial polar surface in a portion thereof, and either cutting the compound single crystal layer that has been grown in parallel to the basal plane, or removing at least said substrate to obtain a compound single crystal block, a basal plane of which is a nonpolar face only having a partial polar surface with the highest surface energy in a portion thereof.
The present invention still further relates to a laminate having, on the basal plane of the above-me
Kawahara Takamitsu
Nagasawa Hiroyuki
Yagi Kuniaki
Blum David S
Hoya Corporation
Nguyen Tuan H.
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