Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1999-08-30
2002-05-21
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S749000, C438S750000, C438S753000, C438S756000, C438S757000
Reexamination Certificate
active
06391793
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods of semiconductor fabrication. More particularly, the present invention pertains to etching silicon with high selectivity to oxides.
BACKGROUND OF THE INVENTION
There is continued desire for denser integrated circuit devices, e.g., deep submicron technologies. For example, the integration density of memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, ferroelectric (FE) memory devices, etc., continues to increase. Some processes, such as isolation processes, are continuously changing to allow for further reduction in circuit dimensions. For example, despite the advances made to decrease birds peak and channel encroachment problems when local oxidation of silicon (LOCOS) isolation is used in the fabrication of integrated circuits, such LOCOS techniques may be inadequate for submicron technologies. However, other technologies, such as shallow trench isolation (STI), may fill the need for providing isolation at such submicron dimensions.
For example, generally, in shallow trench isolation, a shallow trench is first etched in the silicon substrate, e.g., at about a 0.3-0.5 micron depth. The shallow trench is then refilled with insulator material, e.g., the trench is filled with silicon dioxide following a short thermal oxidation step used to grow a thin film of thermal oxide on the trench walls to control the silicon/silicon dioxide interface quality. The surface may then be planarized after the trench is refilled to complete the isolation structure.
However, with the use of shallow trench isolation comes a variety of other difficulties, e.g., such as problems associated with the resulting isolation structure or silicon in which it is formed and/or the processes used in forming the trench. For example, in shallow trench isolation (STI) and in the formation of various other integrated circuit structures, it may be desirable to etch silicon at a desirable rate while being highly selective to oxides, e.g., thermal oxide, chemical vapor deposition (CVD) oxide, doped oxides, etc.
Various conventional chemistries have been used to etch silicon. For example, both single crystal and polycrystalline silicon are typically wet etched in mixtures of nitric acid (HNO
3
) and hydrofluoric acid (HF). With use of such etchants, the etching is generally isotropic. The reaction is initiated by the HNO
3
, which forms a layer of silicon dioxide on the silicon, and the HF dissolves the silicon oxide away. In some cases, water is used to dilute the etchant, with acetic acid (CH
3
COOH) being a preferred buffering agent, since it tends to cause less disassociation of HNO
3
and thus yields a higher concentration of the disassociated species. The mixture of such compositions can be varied to yield different etch rates. For example, at high HF concentration and low HNO
3
concentration, the etch rate is controlled by the HNO
3
concentration because in such mixtures there is an excess of HF to dissolve the silicon dioxide created during the reaction of the mixture with the silicon. On the other hand, at a low HF concentration and high HNO
3
concentration, the etch rate is limited by the ability of the HF to remove the silicon dioxide as it is created.
In some applications, it is useful to etch silicon more rapidly along some crystal planes relative to others. For example, in the diamond lattice of silicon, generally the (111)-plane is more densely packed than the (100)-plane, and thus the etch rates of (111) orientated surfaces are expected to be lower than those with (100)-orientations. One etchant that exhibits such orientation-dependent etching properties consists of a mixture of KOH and isopropyl alcohol. For example, such a mixture may etch about one hundred (100) times faster along (100)-planes than along (111)-planes.
However, compositions conventionally used for etching silicon are sometimes undesirable. For example, with respect to HF and HNO
3
, the selectivity to oxides is undesirable, e.g., for some mixtures silicon dioxide actually etches faster than the silicon. Such selectivity characteristics of HF and HNO
3
compositions are undesirable, for example, in shallow trench isolation, when it is desirable to etch silicon while leaving oxide material in the trench for isolation. Further, for example, many conventional silicon etchants leave the surface upon which it contacts undesirably rough and may also be undesirably slow at etching the silicon. For example, an SC-1 solution, which is typically a 5:1:1 solution of deionized water, hydrogen peroxide, and ammonium hydroxide, generally etches silicon at a faster rate than silicon dioxide. However, the etch rate for silicon is undesirably slow. As such, to achieve a desired amount of silicon removal requires a higher temperature or lengthy etch process which may result in an undesirably rough silicon surface.
SUMMARY OF THE INVENTION
There is a need for compositions for etching silicon which have a high selectivity to oxides, and also for a method of using such compositions in the fabrication of integrated circuits. For example, such compositions are particularly useful in conjunction with isolation techniques, e.g., shallow trench isolation. According to the present invention, such an etch composition and methods of using such etch compositions are described herein.
A silicon etching method according to the present invention includes providing a substrate assembly including an exposed silicon region and an exposed oxide region. An etch composition including an ammonium fluoride component, an inorganic acid component, and an oxidizing agent is also provided. The etch composition has a pH in the range of about 7.0 to about 8.0; preferably a pH in the range of about 7.5 to about 7.9. The substrate assembly is exposed to the etch composition.
In various embodiments, the ammonium fluoride component may include ammonium fluoride in a range of about 25 percent to about 40 percent by weight of the etch composition, the oxidizing agent may include hydrogen peroxide in a range of about 5 percent to about 15 percent by weight of the etch composition or ozone in a range of about 1 ppm to about 5 ppm of the etch composition; the inorganic acid may be at least one inorganic acid selected from the group of HF, H
3
PO
4
, H
2
SO
4
, HCl, HNO
3
, and H
2
CO
3
; and the etch composition may have an ionic strength greater than 1, preferably in the range of about 10 to about 100.
Yet in further embodiments, the exposing of the substrate assembly to the etch composition may include etching the exposed silicon region at an etch rate that is greater than about 3 times the etch rate of the exposed oxide region and the etching of the exposed silicon region may be at an etch rate greater than about 9 Å/minute. Preferably, the etched silicon region has a surface roughness in the range of about 1.25 Å RMS to about 1.30 Å RMS.
Another silicon etching method according to the present invention includes providing a substrate assembly including an exposed silicon region and an exposed oxide region and an etch composition comprising ammonium fluoride, an inorganic acid, and an oxidizing agent. The substrate assembly is exposed to the etch composition, wherein exposing the substrate assembly includes etching the exposed silicon region at an etching rate that is greater than about 3 times the etching rate of the exposed oxide region.
In one embodiment of the method, the exposed silicon region may be etched at an etch rate greater than about 9 Å/minute. Further, the etched silicon surface may have a surface roughness in the range of about 1.25 Å RMS to about 1.30 Å RMS.
An etch method for use in forming isolation structures is also described. The method includes providing a silicon substrate and providing an oxide isolation region formed in the silicon substrate. The silicon substrate is etched with an etch composition at an etch rate that is greater than about 3 times an etch rate of the oxide isolation region etched with
Gilton Terry
Lee Whonchee
Pan Pai
Hiteshew Felisa
Micro)n Technology, Inc.
Mueting Raasch & Gebhardt, P.A.
Tran Binh X.
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