Composite wiring layer

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257413, 257755, 257770, H01L 29417, H01L 29423, H01L 2943, H01L 2949

Patent

active

055023240

ABSTRACT:
An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions formed as refractory metal silicide layers on opposite lateral walls of the first conductive portion. Upper surfaces and lateral surfaces thereof are coated with insulating layers formed in separate processes. The insulating layers covering the lateral surfaces in particular are formed by a self-aligning technique requiring no mask process. Where conductive layers are formed over the wiring layer according to this invention, a film forming and patterning process for insulating the conductive portions of the wiring layer is omitted and insulation of the wiring layer is secured.

REFERENCES:
patent: 4780394 (1988-10-01), Blanchard et al.
patent: 4847674 (1989-07-01), Sliwa et al.
patent: 5005068 (1991-04-01), Ikeda et al.
patent: 5031008 (1991-07-01), Yoshida
patent: 5113238 (1992-05-01), Wang et al.
Yang et al., The Impact of Titanium Silicide on the Contact Resistance for Shallow Junction Formed by Out-Diffusion of Arsenic from Polysilicon, Ext. Abstracts of the 1992 Int. Conf. on Solid State Devices and Materials, Tsukuba, 1992, pp. 413-415.
Koyanagi et al., Novel High Density, Stacked Capacitor MOS RAM, Source and Date Unknown.
Chen et al., "A New Device Interconnect Scheme for Sub-Micron VLSI", IEDM 1984, pp. 118-121.

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