Composite mode substrate voltage generation circuit for dynamic

Details Composite mode substrate voltage generation circuit for dynamic Composite mode substrate voltage generation circuit for dynamic

1997-11-07

1999-03-23

Neims, David

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518907, 365222, G11C 1604

Patent

active

058869328

ABSTRACT:
A composite mode substrate voltage generation circuit for a DRAM which has a memory cell block and a peripheral circuit block formed on a single substrate. The circuit comprises a back-bias voltage generator for generating a first back-bias voltage in response to a normal refresh mode control signal or a second back-bias voltage in response to a self-refresh mode control signal and supplying the generated first or second back-bias voltage to the memory cell and peripheral circuit blocks, a first voltage level detector for detecting a level of the first back-bias voltage from the back-bias voltage generator, comparing the detected level of the first back-bias voltage with a first reference voltage level and controlling a voltage pumping operation of the back-bias voltage generator in accordance with the compared result, and a second voltage level detector for detecting a level of the second back-bias voltage from the back-bias voltage generator, comparing the detected level of the second back-bias voltage with a second reference voltage level and controlling the voltage pumping operation of the back-bias voltage generator in accordance with the compared result. A self-refresh operation can stably be performed at low power consumption, resulting in an increase in refresh efficiency of the DRAM.

REFERENCES:
patent: 4985869 (1991-01-01), Miyamoto
patent: 5315557 (1994-05-01), Kim et al.
patent: 5365487 (1994-11-01), Patel et al.
patent: 5426613 (1995-06-01), Takahashi et al.
patent: 5629898 (1997-05-01), Idei et al.

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