Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-17
2003-04-01
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S723000, C438S724000
Reexamination Certificate
active
06541370
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to dielectric layers employed within microelectronic fabrications. More particularly, the present invention relates to crack inhibited dielectric layers employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions and separations have decreased, it has become increasingly difficult to fabricate within microelectronic fabrications microelectronic dielectric layers with enhanced integrity, and in particular enhanced physical integrity. Microelectronic dielectric layers with enhanced integrity are desirable in the art of microelectronic fabrication insofar as microelectronic dielectric layers with enhanced integrity typically provide microelectronic fabrications with enhanced performance and enhanced reliability.
It is thus desirable in the art of microelectronic fabrication to provide within microelectronic fabrications microelectronic dielectric layers with enhanced integrity.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication, for forming, with desirable properties, microelectronic dielectric layers within microelectronic fabrications.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Ravi et al., in U.S. Pat. No. 5,976,993 (a method for reducing intrinsic stress within a high density plasma chemical vapor deposition (HDP-CVD) deposited dielectric layer within a microelectronic fabrication by cycling within a high density plasma chemical vapor deposition (HDP-CVD) method when forming the high density plasma chemical vapor deposition (HDP-CVD) deposited dielectric layer a bias power); and (2) Pangrle et al., in U.S. Pat. No. 6,171,947 (a method for inhibiting stress induced patterned conductor layer/dielectric layer voiding within a microelectronic fabrication by employing a silicon oxynitride liner layer formed upon a patterned conductor layer prior to forming thereupon a gap filling silicon oxide layer).
Desirable in the art of microelectronic fabrication are additional methods for forming within microelectronic fabrications microelectronic dielectric layers with enhanced integrity.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming a dielectric layer within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the dielectric layer is formed with enhanced integrity.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a pair of methods for forming a pair of dielectric layers within a pair of microelectronic fabrications.
To practice a first of the methods of the present invention, there is first provided a substrate. There is then formed upon the substrate a pair of horizontally spaced topographic features. There is then formed upon exposed portions of the substrate and the pair of horizontally spaced topographic features a conformal silicon oxide liner layer formed employing a chemical vapor deposition (CVD) method selected from the group consisting of low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods. There is also formed over the conformal silicon oxide liner layer a gap filling silicon oxide layer formed employing a method selected from the group consisting of sub-atmospheric chemical vapor deposition (SACVD) methods, atmospheric pressure chemical vapor deposition (APCVD) methods and spin-on methods. There is also formed over the gap filling silicon oxide layer a capping silicon oxide layer formed employing a chemical vapor deposition (CVD) method selected from the group consisting of low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods. Finally, there is also formed at least either: (1) interposed between the conformal silicon oxide liner layer and the gap filling silicon oxide layer; (2) interposed between the gap filling silicon oxide layer and the capping silicon oxide layer; or (3) upon the capping silicon oxide layer, at least one stress reducing layer, wherein the at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material.
In accord with a second embodiment of the present invention, there is also first provided a substrate having formed thereupon a pair of horizontally spaced topographic features. However, within the second embodiment of the present invention there is formed upon exposed portions of the substrate and the pair of horizontally spaced topographic features a passivation silicon oxide layer formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. Finally, within the second embodiment of the present invention, there is formed upon the passivation silicon oxide layer a stress reducing layer formed of a silicon and nitrogen containing dielectric material.
The present invention provides a pair of methods for forming a pair of dielectric layers within a pair of microelectronic fabrications, wherein the pair of dielectric layers is formed with enhanced integrity.
The present invention realizes the foregoing object by forming each of the pair of dielectric layers as composite dielectric layers which are otherwise formed of silicon oxide dielectric materials formed at least in part employing chemical vapor deposition (CVD) methods, but having laminated therein at least one stress reducing layer formed of a silicon and nitrogen containing dielectric material. In accord with the present invention, each of the pair of composite dielectric layers so formed exhibits reduced cracking and thus enhanced integrity, due to presence of the stress reducing layers.
The methods of the present invention are readily commercially implemented.
The present invention employs methods and materials as are generally conventional in the art of microelectronic fabrication, but employed within the context of specific structural limitations and specific materials limitations to provide the present invention. Since it is thus at least in part a series of structural limitations and materials limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the methods of the present invention are readily commercially implemented.
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Wolf, S., Silicon Processing for the VLSI Era, vol. 2, Lattice Press, 1999, pp. 273-283.
Chen Shin-Kai
Wang Ming-Tsong
Wang Shi-Wei
Quach T. N.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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