Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-14
2001-09-11
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000
Reexamination Certificate
active
06288423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a memory cell having a composite gate structure or a semiconductor device including a stacked memory cell capacitor and a method of fabricating the same.
2. Description of the Related Art
Conventionally, several improvements have been made to improve the write and erase characteristics of a memory cell of an EEPROM or the like having a floating gate structure or a memory cell capacitor.
As an example, in prior art disclosed in Japanese Patent Laid-Open No. 5-110107, at least a portion of a polysilicon film as a floating gate electrode is formed by CVD under conditions by which a larger number of fine undulations are formed on the surface of the floating gate electrode, and an insulating interlayer and a control gate electrode are formed along the undulations on the surface of the floating gate electrode.
These fine undulations increase the capacitance between the floating gate electrode and a control gate electrode. When voltage drop in which the voltage applied to the control gate electrode decreases occurs, these undulations efficiently act on the floating gate electrode to improve the write and erase characteristics.
Also, in prior art disclosed in Japanese Patent Laid-Open No. 5-55605, a recess is formed in substantially the center of a floating gate electrode to increase the capacitance between the floating gate electrode and a control gate electrode. Consequently, an effect similar to the effect of the above prior art is achieved.
The capacitance of a memory cell capacitor can also be increased by forming undulations on the surface of a lower electrode.
For example, Japanese Patent Laid-Open No. 5-243515 has described a method of increasing the charge storage amount by forming a rectangular or cylindrical trench in a lower electrode of a stacked memory cell capacitor.
Unfortunately, the above-mentioned prior arts have the following problems.
First, in the prior art disclosed in Japanese Patent Laid-Open No. 5-110107, the fine undulations on the floating gate electrode are formed under specific conditions by CVD. Therefore, the fabrication steps are complicated to set the CVD conditions. Additionally, since these undulations are very fine, the effect of increasing the capacitance is not satisfactory.
In the prior art disclosed in Japanese Patent Laid-Open No. 5-55605, the recess is formed in substantially the center of the floating gate electrode after a polysilicon film serving as the floating gate electrode is formed. Therefore, it is unavoidable to complicate the fabrication steps and increase the number of the fabrication steps. Also, the end point of etching for forming the recess is difficult to determine. Accordingly, the recess may sometimes extend through the polysilicon film to separate the floating gate electrode.
In the prior art of a capacitor disclosed in Japanese Patent Laid-Open No. 5-243515, the trench is formed by etching after stacked polysilicon serving as the lower electrode is formed. Accordingly, the fabrication steps are complicated and the number of the fabrication steps is increased. Furthermore, the end point of the etching cannot be easily determined.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which includes a composite gate structure memory cell or a stacked memory cell capacitor, effectively increases the capacitance of the floating gate electrode or the memory cell capacitor, and has high reliability, and a simple method of fabricating this semiconductor device.
A semiconductor device of the present invention is a semiconductor device including an element active region defined by forming an element isolation structure on a semiconductor substrate, comprising an island-like charge storage film formed across the element isolation structure and the element active region so as to be formed on the element active region through an insulating film, the charge storage film having a recess in a surface on the element active region and a hole formed on the element isolation structure to reach the element isolation structure, a dielectric film so formed as to cover the surface of the charge storage film including inner surfaces of the hole, and a conductive film formed on the dielectric film and capacitively coupled with the charge storage film.
Another aspect of the semiconductor device of the present invention is a semiconductor device including an element active region defined by forming an element isolation structure on a semiconductor substrate, comprising an island-like charge storage film formed across the element isolation structure and the element active region so as to be formed on the element active region through an insulating film, the charge storage film having a recess in a surface on the element active region and a hole formed on the element isolation structure to reach the element isolation structure, and a conductive film formed on the charge storage film.
Still another aspect of the semiconductor device of the present invention is a semiconductor device including an element active region defined by forming an element isolation structure on a semiconductor substrate and having a transistor constituted by a gate electrode and a pair of impurity diffusion layers in the element active region, comprising an insulating interlayer formed on the semiconductor substrate including the transistor, a first hole formed in the insulating interlayer and having a surface layer of the impurity diffusion layer as a bottom surface, an island-like charge storage film electrically connected to one of the impurity diffusion layers through the first hole, a second hole formed in the charge storage film and having a surface layer of the insulating interlayer as a bottom surface, a dielectric film so formed as to cover a surface of the charge storage film including inner surfaces of the second hole, and a conductive film formed on the dielectric film and capacitively coupled with the charge storage film, wherein the charge storage film, the dielectric film, and the conductive film constitute a capacitor.
Still another aspect of the semiconductor device of the present invention is a semiconductor device including an element active region defined by forming an element isolation structure on a semiconductor substrate, comprising an insulating film formed on the semiconductor substrate in the element active region, and a charge storage film patterned on the insulating film, wherein the charge storage film is formed across the element isolation structure and has a hole on the element isolation structure, and at least a portion of a bottom surface of the hole reaches a surface layer of the element isolation structure.
Still another aspect of the semiconductor device of the present invention is a semiconductor device including a plurality of element isolation regions defined by forming an element isolation structure on a semiconductor substrate, comprising an island-like charge storage film formed across the element isolation structure and the element active regions and having a recess, a dielectric film so formed as to cover a surface of the charge storage film, and a conductive film formed on the dielectric film and capacitively coupled with the charge storage film, wherein the charge storage film is formed in each of the element active regions, and an upper surface of each of the charge storage films is planarized by CMP and flush with an upper surface of an adjacent charge storage film.
A method of fabricating a semiconductor device according to the present invention comprises the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate, the second step of forming an insulating film on the semiconductor substrate in the element active region, the third step of forming a first conductive film on an entire surface of the semiconductor substrate including the insulating film and the element isolation structure, the fourth step o
Cao Phat X.
Chaudhuri Olik
Connolly Bove Lodge & Hutz
Nippon Steel Corporation
LandOfFree
Composite gate structure memory cell having increased... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Composite gate structure memory cell having increased..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Composite gate structure memory cell having increased... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2463272