Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device
Reexamination Certificate
2007-02-27
2007-02-27
Kebede, Brook (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
C257S310000, C257S388000, C257S412000, C257SE29242, C257SE29272
Reexamination Certificate
active
11158764
ABSTRACT:
An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.
REFERENCES:
patent: 5321289 (1994-06-01), Baba et al.
patent: 5668035 (1997-09-01), Fang et al.
patent: 6013553 (2000-01-01), Wallace et al.
patent: 6015739 (2000-01-01), Gardner et al.
patent: 6030862 (2000-02-01), Kepler
patent: 6166417 (2000-12-01), Bai et al.
patent: 6168958 (2001-01-01), Gardner et al.
patent: 6265325 (2001-07-01), Cao et al.
patent: 6303418 (2001-10-01), Cha et al.
patent: 6383861 (2002-05-01), Gonzalez et al.
patent: 6432776 (2002-08-01), Ono
patent: 6448127 (2002-09-01), Xiang et al.
patent: 6479341 (2002-11-01), Lu
patent: 6495422 (2002-12-01), Yu et al.
patent: 6528374 (2003-03-01), Bojarczuk, Jr. et al.
patent: 6528858 (2003-03-01), Yu et al.
patent: 6621114 (2003-09-01), Kim et al.
patent: 6632714 (2003-10-01), Yoshikawa
patent: 6640403 (2003-11-01), Shih et al.
patent: 6777761 (2004-08-01), Clevenger et al.
patent: 6906398 (2005-06-01), Yeo et al.
patent: 6927414 (2005-08-01), Ouyang et al.
patent: 2004/0198009 (2004-10-01), Chen et al.
patent: 2006/0011949 (2006-01-01), Yang et al.
patent: 2006/0024893 (2006-02-01), Min et al.
patent: 426941 (2001-03-01), None
Chen, C.-H., et al., “Downscaling Limit of Equivalent Oxide Thickness in Formation of Ultrathin Gate Dielectric by Thermal-Enhanced Remote Plasma Nitridation,” IEEE Transactions on Electron Devices, vol. 49, No. 5, May 2002, pp. 840-846.
Yeo, Y.-C., et al., “Direct Tunneling Leakage Current and Scalability of Alternative Gate Dielectrics,” Applied Physics Letters, vol. 81, No. 11, Sep. 9, 2002, pp. 2091-2093.
Mahapatra, R., et al., “ZrO2as a High-k Dielectric for Strained SiGe MOS Devices,” Bull. Mater. Sci., vol. 25, No. 6, pp. 455-457.
Gustafsson, T., et al., “High-Resolution Depth Profiling of Ultrathin Gate Oxides Using Medium-Energy Ion Scattering,” Nuclear Instruments and Methods in Physics Research, B 183, 2001, pp. 146-153
“Bake and Cure of Low-k Dielectric Layers,” Koyo Thermo Systems Co., Ltd., http://www.crystec.com/killowe.htm.
Chen Kuang-Hsin
Han Liang-Kai
Wu I-Lu
Kebede Brook
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Composite gate structure in an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Composite gate structure in an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Composite gate structure in an integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3848481