Composite flag generation for DDR FIFOs

Details Composite flag generation for DDR FIFOs Composite flag generation for DDR FIFOs

2000-03-31

2002-04-23

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S012000, C326S096000, C365S220000, C365S221000

Reexamination Certificate

active

06377071

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to double data rate (DDR) FIFOs generally and, more particularly, to composite flag generation method and/or architecture in DDR FIFOs.
BACKGROUND OF THE INVENTION
Performance in conventional First-in First-out (FIFO) buffers is limited by the speed of the flag logic. A DDR FIFO doubles the performance of a FIFO by internally having two FIFOs running concurrently, offset with a phase difference. A DDR FIFO requires either two slow flags or one fast flag.
Referring to
FIG. 1
, a circuit
10
is shown implementing such a conventional approach. The circuit
10
comprises a clock generation block
12
, a flag block
14
, and a flag block
16
. The clock generation block
12
has an input
18
that receives a free-running read clock signal rCLK, an input
20
that receives an enable signal READENABLE, an output
22
that presents a first free-running read clock signal rCLK
1
, an output
24
that presents a first enabled read clock signal EnrCLK
1
, an output
26
that presents a second free-running clock signal rCLK
2
and an output
28
that presents a second enabled read clock signal EnrCLK
2
. The flag block
14
has an input
30
that receives the signal rCLK
1
and an input
32
that receives the signal EnrCLK
1
. The flag block
16
has an input
34
that receives a signal rCLK
2
and an input
36
that receives the signal EnrCLK
2
. The flag block
14
has an output
38
that presents a first status flag signal FIFO
1
_EF and an output
40
that presents a second status flag signal FIFO
2
_EF.
The two internal slower FIFOs in a conventional DDR FIFO configuration directly present the first and second status flag signals FIFO
1
_EF and FIFO
2
_EF. The overall state of the conventional DDR FIFO is determined by two flags using some sort external glue logic. Simple external AND/OR logic will cause one cycle FIFO flag latency, which will in turn can cause misreads or miswrites at the FIFO EMPTY/FULL boundary.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) one or more first enable signals and (ii) one or more first flag signals in response to a first clock signal and a second enable signal. The second circuit may be configured to generate a second flag signal in response to (i) the one or more first enable signals, (ii) the one or more first control signals, (iii) a second clock signal, and (iv) a pulse signal. The third circuit may be configured to generate the pulse signal in response to (i) a third clock signal and (ii) the one or more first flag signals.
The objects, features and advantages of the present invention include providing a method and/or architecture that may generate flags in a FIFO architecture that may (i) simplify a user interface in a DDR FIFO, (ii) allow faster FIFOs to be implemented in current FIFO architectures, (iii) eliminate the need for external flag glue logic when implementing DDR FIFOs, and/or (iv) generate a single composite empty/full flag that may operate at a DDR FIFO frequency with the same assertion latency as the conventional FIFOs.


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