Composing on-chip interconnects with configurable interfaces

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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C370S401000, C716S030000

Reexamination Certificate

active

07660932

ABSTRACT:
Embodiments of apparatuses, systems, and methods are described for a machine-readable medium having instructions stored thereon, which, when executed by a machine, to cause the machine to generate a representation of an apparatus. The apparatus includes a bridge agent, a first interconnect, and a second interconnect. The bridge agent is configured by bridge control signals to control transmission of a communication between the first interconnect and the second interconnect. The representation may be a sequence of instructions written in a programming language to mimic in a computer simulation environment attributes derived from a projected fabricated hardware instance of the apparatus.

REFERENCES:
patent: 5495605 (1996-02-01), Cadot
patent: 5923860 (1999-07-01), Olarig
patent: 5948089 (1999-09-01), Wingard et al.
patent: 5987541 (1999-11-01), Hewitt
patent: 6034542 (2000-03-01), Ridgeway
patent: 6041400 (2000-03-01), Ozcelik et al.
patent: 6061730 (2000-05-01), Billings
patent: 6081864 (2000-06-01), Lowe et al.
patent: 6122664 (2000-09-01), Boukobza et al.
patent: 6182183 (2001-01-01), Wingard et al.
patent: 6253243 (2001-06-01), Spencer
patent: 6330225 (2001-12-01), Weber et al.
patent: 6336138 (2002-01-01), Caswell et al.
patent: 6539225 (2003-03-01), Lee
patent: 6549516 (2003-04-01), Albert et al.
patent: 6567962 (2003-05-01), Baumgartner et al.
patent: 6571286 (2003-05-01), Fisher et al.
patent: 6578117 (2003-06-01), Weber
patent: 6598207 (2003-07-01), Teague, III
patent: 6654798 (2003-11-01), Skibinski et al.
patent: 6671724 (2003-12-01), Pandya et al.
patent: 6683474 (2004-01-01), Ebert et al.
patent: 6718416 (2004-04-01), Self et al.
patent: 6721793 (2004-04-01), Corless
patent: 6725313 (2004-04-01), Wingard et al.
patent: 6766406 (2004-07-01), Gasperini et al.
patent: 6775719 (2004-08-01), Leitner et al.
patent: 6785256 (2004-08-01), O'Neill
patent: 6785753 (2004-08-01), Weber et al.
patent: 6795857 (2004-09-01), Leung et al.
patent: 6804738 (2004-10-01), Weber
patent: 6804757 (2004-10-01), Weber
patent: 6816814 (2004-11-01), Ebert et al.
patent: 6831916 (2004-12-01), Parthasarathy et al.
patent: 6859931 (2005-02-01), Cheyer et al.
patent: 6880133 (2005-04-01), Meyer et al.
patent: 6948004 (2005-09-01), Gasbarro et al.
patent: 6961834 (2005-11-01), Weber
patent: 6976106 (2005-12-01), Tomlinson et al.
patent: 6996512 (2006-02-01), Alpert et al.
patent: 7120712 (2006-10-01), Wingard et al.
patent: 7194566 (2007-03-01), Wingard et al.
patent: 7356633 (2008-04-01), Weber et al.
patent: 2002/0046260 (2002-04-01), Day, II
patent: 2002/0073338 (2002-06-01), Burrows et al.
patent: 2002/0138287 (2002-09-01), Chen et al.
patent: 2002/0138615 (2002-09-01), Schmeling
patent: 2002/0141401 (2002-10-01), Albert et al.
patent: 2002/0143653 (2002-10-01), DiLena et al.
patent: 2002/0169854 (2002-11-01), Tarnoff
patent: 2002/0184300 (2002-12-01), Schmeling et al.
patent: 2003/0018738 (2003-01-01), Boylan et al.
patent: 2003/0069960 (2003-04-01), Symons et al.
patent: 2003/0074520 (2003-04-01), Weber
patent: 2003/0115559 (2003-06-01), Sawada
patent: 2003/0126192 (2003-07-01), Magnussen
patent: 2003/0158994 (2003-08-01), Moy
patent: 2003/0167144 (2003-09-01), Wang et al.
patent: 2003/0208566 (2003-11-01), Weber et al.
patent: 2003/0208611 (2003-11-01), Weber et al.
patent: 2004/0015961 (2004-01-01), Chefalas et al.
patent: 2004/0223501 (2004-11-01), Mackiewich et al.
patent: 1 376 932 (2004-01-01), None
patent: 03728644 (2005-08-01), None
patent: WO 95/34153 (1995-12-01), None
patent: WO 99/63727 (1999-12-01), None
patent: WO 02/13024 (2002-02-01), None
Cottrell, Donald, Chapter 78: “Design Automation Technology Roadmap”, The VLSI Handbook, Copyright 2000, 41 Pages.
Gupta, Sumit and Gupta, Rajesh K., Chapter 64: “ASIC Design”, The VLSI Handbook, Copyright 2000, 29 pages.
Hurst, Stanley L., Chapter 5: “Computer Aided Design”, VLSI Custom Microelectronics: Digital, Analog, and Mixed-Signal, Copyright 1999, 95 pages.
Hadjitheodosiou, M.H. et al., “Broadband Access Via Satellite”, computer Networks, Elsevier Science Publishers B.V., Amsterdam, NL, vol. 31, No. 4, Feb. 25, 1999, pp. 353-378.
PCT International Search Report No. PCT/US03/13640, 6 pages, mailed Aug. 8, 2003.
United States Patent & Trademark Office, memo from Love, John J., Deputy Commissioner For Patent Examination Policy, entitled, “Clarification of Interim Guidelines For Examination of Patent Applications for Subject Matter Eligibility”, Apr. 12, 2007, 2 pgs.
Wingard, Drew, Declaration of Drew E. Wingard, U.S. Appl. No. 10/138,946, Aug. 2, 2007, 2 pages.

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