Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-11-19
2004-02-10
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S792000, C257S506000, C438S461000, C438S421000
Reexamination Certificate
active
06690081
ABSTRACT:
TECHNICAL FIELD
The present invention is generally related to integrated circuits and, more particularly, is related to compliant wafer-level packaging devices and methods of fabrication thereof.
BACKGROUND OF THE INVENTION
Conventional chip manufacturing is divided into front-end, back-end, and tail-end processing. Front-end processing refers to the fabrication of CMOS transistors, while back-end processing describes wafer metallization. Tail-end processing refers here to the packaging of the individual dies. Generally, the final wafer-level process step is the fabrication of the die pads, which serve as the interface between the die and the package. Each individual die, while still part of the wafer, is then functionally tested to identify known good die (KGD) followed by wafer singulation. The KGD's are then shipped to a packaging foundry where they are individually temporary package for burn-in. The dies that pass this test are then individually packaged into their final package and tested again for functionality. This final step concludes tail-end processing and the functional packaged dies are finally ready for system assembly.
The mechanical performance of a package is important for wafer-level testing, protection, and reliability. Wafer-level testing requires simultaneous reliable contact to all die across a non-planar wafer surface. In-plane (i.e. x-y axis) compliance is generally required to account for potential problems such as, for example, thermal expansion between the chip and printed wiring board and probe contact with leads. Wafer-level testing and burn-in demands significant out-of-plane (i.e., z-axis) compliance in order to establish reliable electrical contract between the pads on the non-planer wafer and pads/probes on the board surfaces. Non-compliance of the input/output (I/O) interconnects/pads out-of-plane, as well as in-plane (i.e., x-y axis), can cause wafer-level testing problems.
Unlike conventional packaging, wafer-level packaging (WLP) is a continuation of integrated circuit manufacturing. In WLP, additional masking steps can be used after fabricating die pads to simultaneously package all dice across the wafer. A unique class of WLP is called compliant wafer-level packaging (CWLP). In CWLP, additional masking steps can be used after fabricating die pads to batch fabricate compliant x-y-z axis I/O leads between the die pads and the board pads. A mechanically x-y-z flexible lead is formed between the die pad and the bump interconnection that would be joined with the board. Accordingly, there is a need in the industry for x-y-z compliant leads that provide high density, high electrical performance, low cost, and ability of batch fabrication. Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
SUMMARY OF THE INVENTION
A representative device of the present invention includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.
The present invention also involves method for fabricating the device described above. A representative method includes: (a) providing a substrate having at least one die pad disposed upon the surface of the substrate; (b) disposing and patterning a first sacrificial polymer layer onto at least one portion of the substrate; (c) disposing an overcoat polymer layer onto the substrate, at least one die pad, and the first sacrificial polymer layer; (d) removing portions of the overcoat polymer layer to expose at least one die pad; (e) disposing a first lead layer onto the at least one die pad and portions of the overcoat polymer layer; and (f) removing the sacrificial layer to define a first air-gap within the overcoat polymer layer.
Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.
REFERENCES:
patent: 4827611 (1989-05-01), Pai et al.
patent: 5757072 (1998-05-01), Gorowitz et al.
patent: 5864946 (1999-02-01), Eldridge et al.
patent: 6080603 (2000-06-01), Distefano et al.
patent: 6136212 (2000-10-01), Mastrangelo et al.
patent: 6165890 (2000-12-01), Kohl et al.
patent: 6221750 (2001-04-01), Fjelstad
Bakir; Reed; Mul′; Kohl; Martin; and Meindl; Sea of Leads (SoL.) Ultra High Density Compliant Wafer Level Packaging Technology; Unpublished to date.
Reed; Bakir; Patel; Martin; Meindl; and Kohl; Compliant Wafer Level Package (CWLP) with Embedded Air-gaps For Seal of Leads (SoL) Interconnections; Proc. IEEE International Interconnect Technology Conference. S an Francisco, CA: pp. 151-153; Jun. 2001.
Bakir; Reed; Kohl; Martin; and Meindl; Sea of Leads Ultra High-Density Complaint Wafer-Level Packaging Technology; Unpublished to date.
Bakir; Reed; Mule'; Kohnl; Martin; and Meindl; Sea of Leads (SoL) Characterization and Design for Compatibility With Board-Level Optical Waveguide Interconnection; Unpublished to date.
Bakir Muhannad S.
Kohl Paul
Martin Kevin P.
Meindl James
Patel Chirag S.
Everhart Caridad
Georgia Tech Research Corporation
Thomas Kayden Horstemeyer & Risley LLP
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