Compliant semiconductor chip assemblies and methods of making sa

Details Compliant semiconductor chip assemblies and methods of making sa Compliant semiconductor chip assemblies and methods of making sa

1996-09-05

2000-02-01

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

438118, H01L 2144

Patent

active

060202203

ABSTRACT:
A semiconductor chip package assembly is mounted to contact pads on a die. A compliant interposer layer is disposed between the die and a dielectric substrate wiring layer. The contacts on the die are connected to terminals on the compliant interposer layer by means of a compliant, conductive polymer extending through apertures in the interposer layer. Compliancy in the interposer layer and in the conductive polymer permits relative movement of the terminals on the dielectric substrate wiring layer to the contacts on the die and hence relieves the shear forces caused by differential thermal expansion. The arrangement provides a compact packaged structure similar to that achieved through flip-chip bonding, but with markedly increased resistance to thermal cycling damage. Further, the packaged structure allows the standardization of the packages such that several companies can make competing chips that are packaged such that the resultant packaged structures are roughly the same as far as the end user is concerned.

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