Compliant lead structures for microelectronic devices

Details Compliant lead structures for microelectronic devices Compliant lead structures for microelectronic devices

1999-03-30

2001-04-10

Williams, Alexander O. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S690000, C257S673000, C257S674000, C257S669000, C257S696000

Reexamination Certificate

active

06215191

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the packaging of microelectronic devices, and more particularly to a method of treating a conductive lead for a semiconductor chip package.
BACKGROUND OF THE INVENTION
Modem electronic devices utilize microelectronic devices and semiconductor chips (generically referred to herein as “chips”) which incorporate numerous electronic elements. These chips are mounted on circuitized substrates which provide physical support and further electrically interconnect each chip with other elements of the circuit. A discrete chip package, equipped with terminals for interconnection to the external circuit elements, may be used to hold a single chip. Alternatively, in a so-called “hybrid circuit”, one or more chips are mounted directly to a package forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with a reliable electrical interconnection to the substrate. The interconnection between the chip itself and its package is commonly referred to as “first lever assembly or chip interconnection, as distinguished from the interconnection between the package and the other elements of the circuit, commonly referred to as a “second level” interconnection.
The structures utilized to provide the first level connection between the chip and the package must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial numbers of I/O connections.
The first level interconnection structures connecting a chip to a substrate ordinarily are subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperatures of the chip and substrate rise each time the device is turned on and fall each time the device is turned off. As the chip and the substrate ordinarily are formed from different materials having different thermal coefficients of expansion (“TCE”) and because all of the heat will be generated within the chip and not within the substrate, the chip and substrate expand and contract by different amounts and at different times. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress. Such thermal cycling stresses are applied repeatedly with repeated operation of the device, and can cause electrical and mechanical failure of the interconnections.
The thermal stresses at the first level interconnection are exacerbated when a chip size package is used. A chip size package is typically a package which is attached to and fits on the face surface of the operational portion of a chip. In such a package, all of the package dimensions are reduced thereby reducing the first level interconnection features which traditionally have absorbed much of the thermal cycling stresses. As a result, these interconnection features are placed under substantially more stress and strain and it becomes very important to have features which minimize the size of the package while simultaneously maximizing the compliancy of the first level interconnection. This is also true for chip scale packages which are typically just slightly larger than the operational portion of the chip. Commonly assigned U.S. Pat. No. 5,148,265 discloses improvements in semiconductor chip assemblies and methods of making the same. As more fully set forth in the '265 patent, a semiconductor chip having peripheral contacts and a central region of the chip disposed inwardly from the peripheral contacts is connected to a sheet-like dielectric, and preferably flexible, interposer. The interposer overlies the central region of the contact bearing surface of the chip. A first surface of the interposer faces towards the chip whereas a second surface faces away from the chip. The interposer further has outward edges disposed inwardly of the peripheral contacts on the chip. Terminals are disposed on the second surface of the interposer overlying the central portion of the chip such that the terminals are exposed at the second surface for interconnection to a substrate. Typically, these terminals will be bonded to a substrate by a surface mount soldering process. A conductive lead extends from at least some of the terminals to an outward edge of the interposer. The connection sections of the leads further extend beyond the edge and are connected to one of the peripheral contacts. The connection sections of the leads flex and/or distort in response to thermal cycling stress due to operation of the chip thereby allowing the central terminals to be moveable with respect to the chip contacts providing excellent resistance to the thermal stress problem. The package described in the '265 patent may also include a compliant layer disposed between the first surface of the interposer and the top surface of the chip.
Typically, the most cost effective method of creating the leads on such a package is to plate metal in circuit patterns within defined areas on a surface of the interposer. After the lead plating operation, a bonding gap is removed from the dielectric material of the interposer. The interposer can then be juxtaposed with the chip and a bonding tool can be used to shape and bond the leads to contacts on the face of the chip within the bonding gap using thermocompression, ultrasonic energy or a combination thereof. However, typical plating processes create porous, coarse grained lead structures having large, non-planar surface variations. In fact, the density of the plated leads ranges from about 90 to 98 percent due to the porosity problem. During operation of the packaged chip, the leads have high stress regions due, in part, to the coarse grain and the porosity of the plated leads, both of which serve as sites which weaken the lead and accelerate fatigue fractures. As chip packages are made smaller and thus the dimensions of the package's leads are likewise made smaller, the surface non-planarities and the lead porosity due to the plating operation also become a larger factor in obtaining a good intermetallic bond between a lead and its respective chip contact. As mentioned above, the leads are typically bonded using a combination of heat, force and/or ultrasonic energy over time. A lead which has large surface variations will be more difficult to bond without causing a weak portion of the lead at the outer edge of the bond. Another problem caused by the surface variations is the difficulty in obtaining a uniform bond between the lead and a chip contact so that Kirkendahl voiding problems do not occur to weaken the bond, as described in more detail below.
In attempting to achieve high plating speeds for mass production of parts, plating operations also typically leave contamination on the surface of the leads and in the grain boundaries of the leads. Common reasons for contamination of the leads are poor quality control in the plating baths (thus allowing stray contaminates from sources such as photoresist breakdown, etc.), grain refining additives intentionally placed in the solutions (such as thallium, arsenic, or lead) which may co-deposit themselves with the plated metal, and (in the case of gold plating baths) from a concentration of cyanide and cyanide polymers due to the replenishment of potassium gold cyanide. Further, hydrogen (which is a possible by product of gold plating) entrapment increases the hardness of plated gold. There are other reasons for such contamination which are too

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