Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2003-03-04
2004-10-26
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189011, C365S189040
Reexamination Certificate
active
06809979
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to dynamic random access memory (DRAM), particularly to three-transistor (3T) DRAM.
BACKGROUND
Various forms of static and dynamic semiconductor storage cells are known in the art. Static cells (usually 6T-SRAM) continue to store data for as long as power is applied to them. In contrast, a dynamic storage cell (e.g., 1T-DRAM, 3T-DRAM or 4T-DRAM) must be periodically refreshed or it loses the stored data. Static cells are generally faster, consume less power and have lower error rates, but have the disadvantage of requiring more space on a semiconductor chip. Generally speaking, refreshing scheme on the dynamic storage cells only creates the pseudo static storage cells because the external access command is unpredictable and can't be executed when the heavy external access occurs and interferes with the internal refresh operation. One way to solve the access/refresh conflict problem is to insert the refresh operation after the external access operation in the same clock cycle but it causes more cycle time or poorer performance.
Various conventional circuitries use the dynamic storage cells but provide the static storage effect to reduce the space on the semiconductor chip. 4-T SRAM cell is given a higher leaky current from the pre-charged bit line to the storage node via the pass transistor to retain the data. 1T-DRAM is the smallest in area but the capacitor included in the memory cell has a three-dimensional configuration that increases the process numbers and the production cost. Moreover, because of the required destructive read and write-back, access time is increased when compared with a case in which 6T-SRAM is employed. As such, these are not suitable for system-on-chip (SOC) applications since most of these SOC applications use the generic process provided by the majority of the foundries.
A three-transistor DRAM (3T-DRAM) cell (see
FIG. 1
) is not required to conduct the process to form a capacitor having a three-dimensional structure and can be fabricated in the same transistor processes as for the memory including 6T-SRAM. The access speed can be similar to the 6T-SRAM since the 3T-DRAM read operation is non-destructive. However, 3T-DRAM has the drawback of needing more frequent refresh operations to retain the data due to a small storage capacitance in the memory cell. This increases the possibility of conflict between an access to the 3T-DRAM cell for external access and an internal access for the refresh operation. Thus, for 3-T DRAM, a need exists to have internal refresh operation running independently in the memory block no matter what the external access is, such that the speed advantage of 6T-SRAM and the area advantage of DRAM can be obtained at the same time.
REFERENCES:
patent: 5812476 (1998-09-01), Segawa
patent: 5995433 (1999-11-01), Liao
patent: 6671210 (2003-12-01), Watanabe et al.
Elms Richard
Fernandez & Associates LLP
Fernandez & Associates, LLP
Luu Pho M.
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