Complementary source coupled logic

Details Complementary source coupled logic Complementary source coupled logic

1999-11-23

2001-11-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S126000, C326S127000, C326S112000

Reexamination Certificate

active

06320422

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to differential logic circuits and, more particularly, to differential logic circuits suitable for low voltage differential signaling.
2. Description of the Related Art
Electrical circuits have used differential logic circuits for many years. Early single-ended bipolar digital logic families, such as Resistor-Transistor Logic (RTL), Diode-Transistor Logic (DTL), and Transistor-Transistor Logic (TTL), which made use of a saturating transistor inverter and large signal swing, exhibited large propagation delay time because of their saturation delay time. To overcome the saturation delay, differential logic families based on non-saturating current switches and low signal swing, such as Current Mode Logic (CML), Emitter Coupled Logic (ECL), and Positively-referenced Emitter Coupled Logic (PECL), have been widely used in bipolar integrated circuits. CML is the simplest form of differential logic in bipolar integrated circuits. The poor capacitive drive of CML was later overcome in ECL by coupling the differential output by an emitter follower.
The counterparts of CML and ECL in bipolar integrated circuits are obtainable in Complementary Metal Oxide Semiconductor (CMOS) integrated circuits, and they are referred to as Current Mode Logic (CML) and Source Coupled Logic (SCL), respectively.
FIG. 1
is a schematic diagram of a conventional n-type SCL circuit
100
. The n-type SCL circuit
100
is composed of n-type CML differential pair and two n-type single-ended source followers. The n-type CML differential pair includes transistors
102
and
104
, load transistors
106
and
108
, and a current source (Is). The transistors
102
and
104
are coupled to a supply voltage (V
DD
) through the load transistors
106
and
108
. The transistors
102
and
104
receive a differential input (IN+ and IN−). The load transistors
106
and
108
are biased by a bias voltage signal. The current source (Is)
110
couples the commonly connected sources of the transistors
102
and
104
to ground. A first of the n-type single-ended source followers includes a transistor
112
and a current source (Is)
114
, and a second of the n-type single-ended source followers includes a transistor
116
and a current source (Is)
118
. Similarly, the p-type SCL is composed of a p-type CML differential pair and two p-type source followers.
Both CML and SCL operate with low signal swing as required for high-speed operation. The SCL may potentially operate at higher speed since the source followers in SCL isolate the capacitive loading from the drains of CML differential pair. Furthermore the SCL is well suited for driving large impedance loads because of its low output impedance.
FIG. 2
is a schematic diagram of a low-voltage variable-delay gain stage circuit
200
that is known in the art. The low-voltage variable-delay gain stage circuit
200
is a Complementary Metal Oxide Semiconductor (CMOS) device that can operate at lower operating voltages than could earlier designs due to the PMOS load biased by NMOS source follower and the folded PMOS control stage to avoid stacking.
The low-voltage variable-delay gain stage circuit
200
uses NMOS source followers
202
and
204
which bias load transistors
206
and
208
(p-type transistors), respectively. Further, the low-voltage variable-delay gain stage
200
includes a differential pair including n-type transistors
210
and
212
. The transistors
210
and
212
form a differential pair and have their sources commonly coupled to ground through a current source
218
. The outputs for the low-voltage variable-delay gain stage
200
are obtained from the drains of the transistors
210
and
212
of the differential pair. The low-voltage variable-delay gain stage
200
also includes gain-control circuitry
220
. Here, the cross-coupled transistors
222
and
224
biased by current source
226
introduce a negative resistance equal to −2/g
m
, where g
m
denotes the average transconductance of transistors
222
and
224
. This negative resistance partially cancels the resistance at the drain of the load transistors
206
and
208
, increasing the effective output impedance and hence the delay. Transistors
228
and
230
receive a control voltage and change the amount of current flowing through the transistors
210
and
212
versus transistors
222
and
224
.
The low-voltage variable-delay gain stage
200
uses PMOS loads (i.e., p-type load transistors
206
and
208
) biased by NMOS source follower (i.e., n-type transistor
202
and
204
). The advantage of the use of the NMOS source followers to bias the PMOS loads, as opposed to a constant reference voltage being used to bias the loads, is that an extended constant R
on
is maintained across the load transistors
206
and
208
in the triode region. The outputs are obtained from the drains of the differential pair (
210
and
212
), and thus, the logic topology of the low-voltage variable-delay gain stage
200
is CML.
The CML and SCL topologies are applicable to both intra-chip building blocks and inter-chip interface. When CML and SCL are used for interface, they require impedance matched loads terminated to a fixed voltage. More recently, the Low Voltage Differential Signaling (LVDS) standard has been developed to provide yet another form of differential interface. LVDS requires impedance-matched loads only, and does not require a fixed termination voltage. Thus, LVDS can be used between a transmitter and a receiver that have ground shift. However, the ground shift imposes that the receiver should accommodate the input common mode variation resulting from it. The current LVDS standard specifies that the DC level of the receiver output is at 1.2V and ground shift up to ±1.2V is allowed, which impose minimum 0 to 2.4V of input common mode range at the receiver. This common mode range is almost equivalent to rail-to-rail in 2.5V supply.
The differential pairs in CML or SCL have limited input common-mode range. The n-type differential pair operates from V
TN
to V
DD
and the p-type differential pair operates from V
SS
to V
DD
−V
TP
, where V
DD
and V
SS
are supply voltage voltages and V
TN
and V
TP
are threshold voltages of the n-type and p-type transistors, respectively. In order to accommodate the rail-to-rail input common mode range, both n-type and p-type differential pairs are often used and the output signals of both pairs should be combined.
The conventional approach to combine the outputs of an n-type and a p-type differential pair is to mirror the currents of one type and add the current to a summing node. This approach is applicable only to CML, but not to SCL without loss of bandwidth. Thus, there is a need for ways to combine the outputs of n-type and p-type SCL pairs.
SUMMARY OF THE INVENTION
Broadly speaking, the invention relates to a Complementary Source Coupled Logic (CSCL) topology suitable for low voltage differential signaling. The Complementary Source Coupled Logic topology is referred to as Complementary Source Coupled Logic as it contains both n-type and p-type Source Coupled Logic (SCL) topology. The CSCL topology can be used to form any differential Boolean logic design, but is particularly well suited for buffering small signal differential signals with large input common-mode range.
The invention can be implemented in numerous ways, including as a computer system, an apparatus, and a method. Several embodiments of the invention are discussed below.
As a differential circuit having a high bandwidth over a rail-to-rail common mode range, one embodiment of the invention includes: a first differential pair receiving first and second differential inputs; a first pair of active loads coupled between said first differential pair and a first power source; a first current source coupled between the first differential pair and a second power source; a second differential pair receiving the first and second differential inputs; a second pair of active loads coupled between the sec

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