Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent
1986-06-13
1989-10-10
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
365190, 36523004, G11C 700, G11C 1140
Patent
active
048736708
ABSTRACT:
A semiconductor memory device has first and second power terminals, a plurality of MOS transistors as memory cells, a plurality of word lines respectively connected to the gates of the MOS transistors, and a bit line connected to one end of the current path of each of the MOS transistors. The other end of the current path of each of the MOS transistors is selectively connected to either the first or second power terminal, in accordance with data to be stored.
REFERENCES:
patent: 3648071 (1972-03-01), Mrazek
patent: 4434381 (1984-02-01), Stewart
patent: 4541077 (1985-09-01), Rupp
patent: 4575823 (1986-03-01), Fitzpatrick
patent: 4597063 (1986-06-01), Takemae
patent: 4646264 (1987-02-01), Matsuzaki
patent: 4658380 (1987-04-01), Eby
patent: 4710789 (1987-12-01), Furutani et al.
Mazin et al., "A Modular Memory Building Block Approach for VLSI", IEEE 1985 Custom Integrated Circuits Conference, pp. 258-263.
Haraszti, "Novel Circuits for High Speed ROM's", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 2 (Apr. 1984); pp. 180-186.
Hashimoto Hideo
Tanaka Yasunori
Bowler Alyssa H.
Hecker Stuart N.
Kabushiki Kaisha Toshiba
Tosbac Computer System Co., Ltd.
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