Complementary semiconductor memory device

Details Complementary semiconductor memory device Complementary semiconductor memory device

1987-12-04

1989-08-01

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365190, 365206, 365210, G11C 1140, G11C 700

Patent

active

048538973

ABSTRACT:
The invention discloses a semiconductor memory device possessing high operational reliability. In the semiconductor memory device according to the invention, a plurality of well regions of a conductivity type different from that of a semiconductor substrate are formed in the semiconductor substrate, and a memory cell array and a bit line driver are formed in other well regions, situated away from each other. With this arrangement, the number of signal lines to be connected to the well region in which the memory cell array is formed can be reduced, and the adverse influence of minority carriers generated upon operation of the bit line driver can be prevented. With this arrangement, well bias can be applied only to memory cell array. As a result, the operational reliability of the semiconductor memory device can be improved.

REFERENCES:
patent: 4399519 (1983-08-01), Masuda et al.
patent: 4472792 (1984-09-01), Shimohigashi et al.
Suzuki et al., "A 128K Word.times.8 Bit Dynamic RAM," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 624-627, Oct. 1984.
Taylor et al., "A 1 Mb CMOS DRAM with a Divided Bitline Matrix Architecture," IEEE International Solid-State Circuits Conference, ISSCC Digest of Technical Papers, pp. 242-243, Feb. 1985.
Mohsen et al., "The Design and Performance of CMOS 265K Bit DRAM Devices," IEEE Journal of Solid-State Circuits, vol. 19, No. 5, Oct. 1984.
Wang et al., "A 21 ns 38K.times.8 CMOS SRAM With a Selectively Pumped P-Well Array," IEEE International Solid-State Circuits Conference, ISSCC Digest of Technical Papers, pp. 254-255, Feb. 1987.

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