Complementary semiconductor devices

Details Complementary semiconductor devices Complementary semiconductor devices

1998-04-29

2001-10-16

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S107000, C257S133000, C257S338000

Reexamination Certificate

active

06303961

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to a metal-oxide semiconductor device that has an improved compatibility for use in a CMOS device and may be integrated on a chip with a DMOS of opposite-type conductivity.
BACKGROUND OF THE INVENTION
The metal-oxide semiconductor field effect transistor (MOSFET) is a dominant and important device in fabricating very large-scale integrated circuits, and various types of MOSFETS are known. MOSFET technology basically can be categorized as consisting of NMOS and CMOS technology, the former comprising n-channel MOS devices and the latter comprising n-channel and p-channel devices integrated on the same chip. Other acronyms are used to identify MOSFETs, including DMOS (wherein “D” stands for “diffusion” or “double diffusion”), PMOS (p-channel MOS), IGBT (Insulated Gate Bipolar Transistor), BiCMOS (CMOS having bipolar devices), and DGDMOS (Dual Gate DMOS). Following accepted terminology, the term CMOS denotes that n-channel and p-channel devices are integrated simultaneously on the same chip, and the term CMOS is so used herein.
Various types of semiconductor devices, as well as both n-channel and p-channel devices, may be integrated within a single semiconductor chip. This is made possible by use of device structures and processes which are compatible with the different types of devices included on the chip. However, designing the devices to achieve compatibility typically means that performance of each of the devices will be less than optimal. CMOS devices provide significant advantages in terms of their low power consumption, but they generally require more complex processing as compared with NMOS devices. Also, with present technology, CMOS structures have been confined to low voltage devices operable at less than 5V. N-channel DMOS or IGBT devices operating at medium (10-100) and high (>100) voltages may be made to be complementary with p-channel DMOS devices, but presently this is achieved by separately fabricating the complementary p-channel devices, using different processing steps, which then may be coupled to the n-channel devices. These are not CMOS devices in that they are not integrated simultaneously on one chip.
To illustrate, referring to
FIG. 1A
, there is shown a cross-sectional view of a prior art n-channel MOS device, without double diffusion. The characteristic features of this basic device comprise a p-type semiconductor substrate
12
having a major surface
14
, within which are disposed two n+ regions or bodies
16
a
,
16
b
, forming a source and drain, respectively. Overlying the surface
14
is a gate electrode
20
, typically fabricated with polysilicon or a combination of polysilicon and silicide (MoSi
2
), separated from surface
14
by a layer of gate oxide
22
. Field oxide layer
24
isolates the source and drain, and a protective layer of glass
34
, typically boron phosphorus silicate glass, is disposed over the device. A further silicon nitride layer (not shown), may be disposed over the glass. The channel
23
is defined by the upper portion of the substrate
12
, which underlies gate
20
.
FIG. 1A
shows an n-channel device (NMOS), but a p-channel device (PMOS) may be formed following the same schematic by substituting p for n and reversing the polarity of the charges.
FIG. 1B
illustrates a basic CMOS structure involving NMOS and PMOS devices integrated on the same chip, following the structure for the MOS of FIG.
1
A and using like character numerals to refer to like features. Metallization region
35
, typically fabricated with aluminum, may be deposited over the device and etched as desired (as shown), for interconnection of the device structures. The gate of the NMOS device
30
may be connected to the gate of the PMOS device
40
. For example, a conductive conduit
38
, having contact V
G
, is shown schematically with hatched lines interconnecting the gates. In processing this CMOS, a p-tub or well
18
is implanted in the n-substrate, enabling formation of the complementary devices in substrate
12
. Separate implantation steps are required for forming the p-tub
18
, the n+ source and drain regions
16
a
,
16
b
, and the p+ source and drain regions
16
c
,
16
d
; p-type regions generally are formed by implantation with boron ions, and n-type regions by implantation with arsenic or phosphorus ions. Because of the p-tub
18
and the processing needed to make the PMOS, the number of steps for fabricating the basic CMOS of
FIG. 1B
is essentially double that for the NMOS of FIG.
1
A.
Referring now to
FIG. 2A
, there is shown a basic embodiment of a double-diffused, n-channel MOS, again with like numerals used to refer to like features as compared with
FIGS. 1A-1B
. Substrate
12
of n-type conductivity is disposed within a chip
100
and isolated from it by a layer of dielectric material
102
, such as silicon dioxide. The substrate
12
has a major surface
14
on which active components are disposed, e.g., gate electrode
20
insulated by gate oxide layer
22
. The device here shown comprises spaced-apart, plural source regions connected in parallel. Source regions comprise first doped regions
17
of n-type conductivity, connected by source electrodes
21
, and second doped regions
19
of p-type conductivity formed within substrate
12
. A region of p+ type conductivity
25
may be implanted beneath source contacts
21
, interposed between each of the doped bodies comprising the source regions, as also described in U.S. Pat. No. 5,541,429, “Dielectrically Isolated Semiconductor Devices Having Improved Characteristics,” issued Sep. 17, 1996 to M. A. Shibib, the inventor herein, assigned to AT&T Corp., a predecessor of the assignee herein, which is incorporated herein by reference.
The second doped regions
19
extend further laterally under gate electrode
20
than first doped regions
17
. The portions
23
of the second doped regions
19
extending beyond the first regions
17
beneath the gate oxide comprise the channel regions of the device, and the substrate beneath the surface portion comprises a drain region. Also, a doped body
26
of n+ conductivity forms a supplemental drain region in contact with drain electrode
27
. A heavily-doped region
28
may extend laterally along the bottom of the substrate and then vertically upwardly to drain electrode
27
. This channel
28
provides a low resistance path for current to the drain electrode for controlling the current as the DMOS devices typically are used in applications involving high voltages and currents.
The Insulated Gate Bipolar Transistors (IGBT) can be identical to the DMOS devices illustrated in
FIG. 2A
, except that certain high conductivity regions are of opposite type conductivity to that of the substrate
12
. For example,
FIG. 3A
shows a prior art n-channel IGBT device, wherein doped regions
76
,
77
are of opposite conductivity to the substrate. Further background concerning MOS devices and the various structures that may be used can be found in the following U.S. patents, all of which issued to the inventor herein, Muhammed Ayman Shibib, were assigned to the present assignee or its predecessor in interest, and are hereby incorporated herein by reference: U.S. Pat. No. 5,670,396, “Method of Forming a DMOS Controlled Lateral Bipolar Transistor,” issued Sep. 23, 1997; U.S. Pat. No. 5,557,125, “Dielectrically Isolated Semiconductor Devices Having Improved Characteristics,” issued Set. 17, 1996; U.S. Pat. No. 5,541,409, cited above; U.S. Pat. No. 5,395,776, “Method of Making a Rugged DMOS Device,” issued Mar. 7, 1995; U.S. Pat. No. 5,381,031, “Semiconductor Device With Reduced High Voltage Termination Area and High Breakdown Voltage,” issued Jan. 10, 1995. Bipolar CMOS devices are further described in M. Ayman Shibib & G. T. Jones, “A Cost Effective Smart Power BiCMOS Technology,” Proceedings of 1995 International Symposium on Power Semiconductor Devices & IC (1995) (hereinafter the “Symposium article”), also incorporated herei

Affiliated with

Also associated with

Rating

Complementary semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Complementary semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary semiconductor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2583077