Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-31
2004-08-17
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S359000, C257S363000, C257S369000, C257S379000, C257S380000
Reexamination Certificate
active
06777752
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which a low voltage operation, low power consumption and a high driving capacity are required, particularly to a power management semiconductor device such as a voltage detector (hereinafter referred to as VD), a voltage regulator (hereinafter referred to as VR) or a switching regulator (hereinafter referred to as SWR) or an analog semiconductor device such as an operational amplifier or a comparator.
2. Description of the Related Art
FIG. 89
is a schematic cross sectional view of a conventional semiconductor device. The semiconductor device is composed of a complementary MOS structure (hereinafter referred to as NMOS) in which a gate electrode formed on a P-type semiconductor substrate is comprised of N+ type polycrystalline silicon and a P-channel MOS transistor
212
(hereinafter referred to as PMOS) in which a gate electrode formed in an N-well region is also comprised of N+type polycrystalline silicon, and a resistor
215
used in a voltage dividing circuit for dividing a voltage which is formed on a field insulating film or a CR circuit for setting a time constant. The resistor is formed of a polycrystalline silicon that is the same layer as a gate electrode of CMOS with N-type conductivity and has the same conductivity type in terms of simplicity and ease of a method of manufacturing thereof.
In the semiconductor device with the above conventional structure, since an enhancement type NMOS (hereinafter referred to as E-type NMOS) with a voltage of approximately 0.7 V that is a standard threshold voltage has a gate electrode comprised of N+polycrystalline silicon, a channel is a surface channel formed on a surface of a semiconductor substrate in accordance with the relationship of working functions of the gate electrode and the semiconductor substrate. On the other hand, in an enhancement type PMOS (hereinafter referred to as E-type PMOS) with a voltage of approximately −0.7 V that is a standard threshold voltage, a channel is a buried channel somewhat formed in an inner side from the surface of the semiconductor substrate in accordance with the relationship of working functions of the gate electrode comprised of N+polycrystalline silicon and the N-well.
In the buried channel E-type PMOS, in the case where the threshold voltage is set to, for example, −0.5 V or more for low voltage operation, a subthreshold characteristic, which is one index of low voltage operation of a MOS transistor, extremely deteriorates, and thus, a leak current at the off time the PMOS increases. As a result, consumption current at the time of waiting of the semiconductor device remarkably increases. Thus, there is a problem in that it is difficult to apply the semiconductor device to portable apparatuses typified by a portable telephone and a portable terminal which are greatly demanded in recent years and the market for which is predicted to further develop in the future.
As technical means for attaining the above-described problems, both the low voltage operation and the low consumption current, the homopolar gate technique is generally known, in which the conductivity type of an NMOS gate electrode is set as N-type and the conductivity type of a PMOS gate electrode is set as P-type. In this case, both the E-type NMOS and the E-type PMOS are surface channel MOS transistors, and therefore, the lowering of the threshold voltage does not lead to the extreme deterioration of a sub-threshold coefficient. Thus, the low voltage operation and the low power consumption are possible.
However, the homopolar gate CMOS has a problem in that increases of the number of steps, the manufacturing cost, and the manufacturing period are caused in comparison with the CMOS in which the gate electrode is only N+polycrystalline silicon monopole since the gate polarities are separately formed for the NMOS and PMOS in the manufacturing process.
Further, a reference voltage circuit is given as an important element circuit constituting a power management semiconductor device such as VD, VR and SWR. The reference voltage circuit always outputs a constant voltage from an output terminal with respect to the electric potential of a low voltage supply terminal irrespective of the electric potential of a high voltage supply terminal. The reference voltage circuit is constituted of an E-type NMOS and a depletion type NMOS (hereinafter referred to as D-type NMOS) with series connection in many cases. In the case where the polarity of the gate electrode is N-type, the E-type NMOS is a surface channel while the D-NMOS is a buried channel in accordance with the relationship of working functions of the gate and the well or substrate. As an important characteristic of the reference voltage circuit, there is given a small change of an output voltage to a change of temperature. However, the threshold voltage of MOS and the degree of change to the temperature change of mutual conductance are largely different between the surface channel and the buried channel. As a result, the reference voltage circuit has a problem in that it is difficult to reduce the change of an output voltage to the temperature change.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above, and an object of the present invention is therefore to provide a structure that enables the materialization of a power management semiconductor device or an analog semiconductor device in which the low cost, short manufacturing period, low voltage operation and low power consumption are attained.
In order to solve the above-mentioned problems, the present invention employs the following measures.
According to the present invention, there is provided a complementary MOS semiconductor device having an N-channel MOS transistor, a P-channel MOS transistor and a resistor, characterized in that a conductivity type of a gate electrode of the N-channel MOS transistor is P-type, and a conductivity type of a gate electrode of the P-channel MOS transistor is P-type.
Further, according to the present invention, here is provided a complementary MOS semiconductor device, characterized in that the P-type gate electrode of the N-channel MOS transistor and the P-type gate electrode of the P-channel MOS transistor each comprise a single layer of first polycrystalline silicon having a film thickness in a range of 2000 Å to 6000 Å and including boron or BF
2
with an impurity concentration of 1×10
19
atoms/cm
3
or more.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the P-type gate electrode of the N-channel MOS transistor and the P-type gate electrode of the P-channel MOS transistor each have a polycide structure comprising a lamination of first polycrystalline silicon having a film thickness in a range of 1000 Å to 4000 Å and including boron or BF
2
with an impurity concentration of 1×10
19
atoms/cm
3
or more and first high melting point metal silicide selected from the group consisting of molybdenum silicide, tungsten silicide, titanium silicide, and platinum silicide, with a film thickness in a range of 500 Å to 2500 Å.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor is polycrystalline silicon formed in the same layer and has the same film thickness range as the first polycrystalline silicon constituting the gate electrode.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor is second polycrystalline silicon having a film thickness in a range of 500 Å to 2000 Å.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor is a thin film metal transistor formed from one selected from the group consis
Hasegawa Hisashi
Ishii Kazutoshi
Koiwa Sumio
Osanai Jun
Adams & Wilks
Seiko Instruments Inc.
Tran Thien F
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