Complementary MOS memory array including complementary MOS memor

Details Complementary MOS memory array including complementary MOS memor Complementary MOS memory array including complementary MOS memor

1978-04-26

1980-02-19

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Flip-flop

307290, 365154, G11C 1140

Patent

active

041897854

ABSTRACT:
A memory array employs a plurality of four-transistor storage cells. Each storage cell includes first and second P channel MOSFETs and first and second N channel MOSFETs. The sources of the first and second P channel MOSFETs are connected to a supply conductor. The drain of the first P channel MOSFET is connected to the drain of the first N channel MOSFET. The drain of the second P channel MOSFET is similarly connected to the drain of the second N channel MOSFET. The gates of the first P channel and first N channel MOSFETs are connected together and to the connected drains of the second P channel and second N channel MOSFETs. The gates of the second P channel and second N channel MOSFETs are connected to the drains of the first P channel and first N channel MOSFETs. The source of the first N channel MOSFET is connected to a row line of the memory array and the source of the second N channel MOSFET is connected to a column line of the memory array. In the array, the memory cells in each row share a respective common first conductor, and all of the memory cells in each column share a common second conductor.

REFERENCES:
patent: 3882467 (1975-05-01), Pricer
patent: 3964031 (1976-06-01), Eaton
patent: 4095281 (1978-06-01), Denes

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