Complementary MOS level translating apparatus and method

Details Complementary MOS level translating apparatus and method Complementary MOS level translating apparatus and method

1998-05-11

2000-09-05

Tokar, Michael

Electronic digital logic circuitry

Interface

Logic level shifting

326 66, 307475, H03K 190175

Patent

active

061148741

ABSTRACT:
A level translating circuit suitable for converting ECL level signals to CMOS level signals. The ECL signal is converted to a pair of buffered differential signals that are level shifted and divided to produce four transistor drive signal, two of which are connected to the respective gate and source of a P-type MOS transistor and two of which are connected to the respective gate and source of another P-type MOS transistor. An N-type transistor is connected in series with each of the P-type transistors so as to provide CMOS outputs at the junction of the N and P-type transistors.

REFERENCES:
patent: 4992681 (1991-02-01), Urakawa et al.
patent: 5304869 (1994-04-01), Greason
patent: 5459412 (1995-10-01), Mentzer
patent: 5502405 (1996-03-01), Williams
Analysis and Optimization of BiCMOS Digital Circuit Structures; S.H.K. Embabi, A. Bellaouar, and, M.I. Elmasry; IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr., 1991; pp. 676-679.
A 7-ns 1-Mb BiCMOS ECL SRAM with Shift Redundacy; Atsushi Ohba, Shigeki Ohbayashi, Toru Shiomi, Satoshi Takano, Kenji Anami, Member IEEE, Hiroki Honda, Yoshiyuki Ishigaki, Masahiro Hatanaka, Shigeo Nagao, and Shimpei Kayano; IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr., 1991; pp. 507-512.

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