Complementary metal oxide semiconductor dual port random access

Static information storage and retrieval – Systems using particular element – Flip-flop

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365190, G11C 1100

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active

045802459

ABSTRACT:
Implemented as a monolithic integrated circuit in CMOS technology, consisting of two two-transistor inverters cross-coupled to form a four-transistor flip-flop memory cell plus an A port NMOS gating transistor connected to one side of the flip-flop and a B port NMOS transistor connected to the other side of the flip-flop. Each A port and B port gating transistor is respectively independently gated by an A port word line and a B port word line addressing signals to conduct the stored contents of the flip-flop respectively to an A port bit line or a B port bit line. The data signal upon each A port bit line and B port bit line is respectively independently gated through respective NMOS transistors by respective A port column address line and B port column address line addressing signals to next be individually compared, in a complementary sense, to a set reference voltage in a respective A port sense amplifier and B port sense amplifier. Reading from either or both the A and B ports is totally independent without conflict. Bit lines are preferably pulled up to the supply voltage. The sense line inputs to the A and B port sense amplifiers are also preferably pulled up to the supply voltage. Writing is by application of equal simultaneous addressing signals on both A and B ports plus the write enabled gating of complementary write data signals, representing the binary quantity to be stored, to each side of the flip-flop memory cell.

REFERENCES:
patent: 4125877 (1978-11-01), Reinert
patent: 4287575 (1981-09-01), Eardley et al.
patent: 4447891 (1984-05-01), Kadota
L. M. Arzubi, "Two-Device Storage Cell", IBM Technical Disclosure Bulletin, vol. 18, No. 3, Aug. 1975, pp. 649-650.

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