Complementary metal-oxide semiconductor buffer

Details Complementary metal-oxide semiconductor buffer Complementary metal-oxide semiconductor buffer

1999-05-03

2001-01-02

Nelms, David (Department: 2818)

Electronic digital logic circuitry

Interface

Current driving

C326S087000

Utility Patent

active

06169421

ABSTRACT:

BACKGROUND OF THE INVENTION
Complementary metal-oxide semiconductor (CMOS) devices are used extensively in digital and analog circuit applications. These devices combine n-channel and p-channel MOS transistors. Typically the p-channel MOS transistor is connected as a load to the drain of the n-channel MOS transistor. CMOS circuits are favored because of their minimal power consumption and high speed. CMOS fabrication technology supports the manufacture of CMOS circuits and their integration on a single chip with other circuits.
It is frequently desirable to have CMOS circuits operate at TTL logic levels. As is known, TTL logic levels underpin widely-accepted standards of digital circuit operation. TTL logic levels implicate a “low” level having a voltage value equal to or less than 0.5 VDC and “high” level of greater than or equal to 2.4 VDC.
Increasingly, CMOS circuitry is used in telecommunications applications. For example, CMOS buffers are employed to drive highly reactive loads such as transmission lines that conduct compressed voice and data signals. In such applications a significant design goal is to provide an output signal that meets the TTL standard in driving a highly reactive load with minimal noise and low power consumption.
SUMMARY OF THE INVENTION
The invention is a complementary metal-oxide semiconductor (CMOS) buffer that accommodates the differences in operational characteristics between a driving circuit and a driven circuit that is highly reactive.
The invention is a CMOS buffer that transfers a TTL-compatible signal between a first circuit and a highly reactive second circuit while isolating the first from the second circuit.
Preferably, the CMOS buffer is a CMOS circuit in an integrated circuit (IC) device.
The CMOS buffer of this invention includes an input inverter having an input and an output. The output of the CMOS inverter is connected to two electrically-parallel CMOS branch circuits. Each branch circuit exhibits a variable delay to signals output by the CMOS inverter: a first delay and a second delay that is longer than the first delay. The branch circuits are connected to a CMOS device comprising an n-channel MOS transistor and a p-channel MOS transistor. A first branch circuit has a connection to the p-channel MOS transistor and the second branch circuit has a connection to the n-channel MOS transistor. The CMOS device has an output. Preferably, the output is connected to an IC pad for driving a transmission line and includes an impedance-matching resistor.
This CMOS buffer embodies the capability of driving a reactive load from an IC location. The CMOS buffer provides an output signal for driving the reactive load, which can be pulled as high as the level of a supply voltage and as low a ground level. The CMOS buffer embodies the capability of driving a transmission line with TTL-compatible signals with low switching noise and low power consumption.


REFERENCES:
patent: 5124578 (1992-06-01), Worley et al.
patent: 5381059 (1995-01-01), Douglas
patent: 5557223 (1996-09-01), Kuo
patent: 6014039 (2000-01-01), Kothandaraman et al.
patent: 6051995 (2000-04-01), Pollacheck

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