Complementary low power non-volatile reconfigurable EEcell

Details Complementary low power non-volatile reconfigurable EEcell Complementary low power non-volatile reconfigurable EEcell

1991-05-10

1993-12-21

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

36518905, 36518909, 365185, G11C 1134

Patent

active

052723682

ABSTRACT:
A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. A CMOS inverter is formed by fabricating an n-channel MOSFET and a p-channel MOSFET with merged floating gate regions. A tunnel capacitor allows charge to be supplied to or removed from the floating gate. The floating gate provides non-volatile charge storage. The CMOS inverter senses the presence or absence of charge on the floating gate and provides an amplified inverted output. The CMOS inverter consumes very low power and provides rail-to-rail output voltage swings.

REFERENCES:
patent: 4858185 (1989-08-01), Kowshik et al.
patent: 5047814 (1991-09-01), Hazani
patent: 5101378 (1992-03-01), Radjy et al.

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