Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2005-11-08
2005-11-08
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S112000, C365S203000
Reexamination Certificate
active
06963228
ABSTRACT:
A complementary input dynamic logic circuit for evaluating a logic function including an N-channel dynamic circuit, a P-channel dynamic circuit and a pass device. The N-channel dynamic circuit determines a complement of the logic function when a clock signal is high by pulling a first evaluation node low if it evaluates. The P-channel dynamic circuit also determines a complement of the logic function when the clock signal is high by pulling a second evaluation node high if the P-channel dynamic circuit evaluates. The pass device is controlled by the first evaluation node and pulls the second evaluation node low if the N-channel dynamic circuit fails to evaluate. An inverted version of the clock signal may be used to drive the second evaluation node low through the pass device. The N- and P-channel dynamic circuits may be implemented with parallel-coupled devices to achieve high fan-in implementations.
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Samuel D. Naffziger, Glenn Colon-Bonet, Timothy Fischer, Reid Riedlinger, Thomas J. Sullivan, and Tom Grutkowski; “The Implementation of the Itanium 2 Microprocessor”; IEEE Journal of Solid-State Circuit; vol. 37, No. 11; Nov. 2002; S.D. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, and T.J. Sullivan are with Hewlett Packard Company, Ft. Collins, CO USA; T. Grutkowski is with the Intel Corporation, Santa Clara, CA 80525 USA.
Cho James H.
Hffman James W.
Huffman Richard K.
IP-First LLC
Stanford Gary R.
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