Complementary field effect transistors having embedded...

Details Complementary field effect transistors having embedded... Complementary field effect transistors having embedded...

2011-06-28

2011-06-28

Roman, Angel (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

With lattice constant mismatch

C257S351000, C257S371000, C257SE27064

Reexamination Certificate

active

07968910

ABSTRACT:
A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.

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