Complementary field-effect transistor logic circuits for wave pi

Details Complementary field-effect transistor logic circuits for wave pi Complementary field-effect transistor logic circuits for wave pi

1994-09-16

1996-06-18

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326114, H03K 1900

Patent

active

055281770

ABSTRACT:
A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and not-invert functions. Each circuit is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.

REFERENCES:
patent: 3943378 (1976-03-01), Beutler
patent: 4541067 (1985-09-01), Whitaker
patent: 4559609 (1985-12-01), Robinson, Jr. et al.
patent: 4607176 (1986-08-01), Burrows et al.
patent: 4620117 (1986-10-01), Fang
patent: 4710649 (1987-12-01), Lewis
patent: 5200907 (1993-04-01), Tran
Neil H. E. Weste, et al, Principles of CMOS VLSI Design-A Systems Perspective, Addison-Wesley Publishing Company, 2nd ed. 1993 AT&T.
Derek Wong, "Techniques for Designing High-Performance Digital Circuits Using Wave Pipeline," Dissertation, Stanford University, 1991.
Bryn Charles Ekroot, "Optimization of Pipelined Processors by Insertion of Combinational Logic Delay," Dissertation, Stanford University, 1987.
K. Shimohigashi, et al., "Low Voltage ULSI Design," IEEE J. of Solid-State Circuits, vol. 28, No. 4 pp. 408-413, Apr., 1993.
R. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Transactions on Computers, vol. C-35, No. 8, pp. 677-691 Aug., 1986.
W. K. C. Lam, et al, "Valid Clocking in Wavepiplined Circuits," 1992 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, pp. 518-525. Nov. 8-12, 1992.
Kazuo Yano, et al., "A 3.8-ns CMOS 16.times.16-b Multiplier Using Complementary Pass-Transistor Logic," IEEE J. of Solid-State Circuits, vol. 25, No. 2, pp. 388-395, Apr., 1990.
Kevin Karplus, "Amap: a Technology Mapper for Selector-based Field-Programmable Gate Arrays" Proceedings of the 28th ACM/IEEE Design Automation Conference, pp. 244-247, Jun. 17-21, 1991.
D. Joy, et al. "Placement for Clock Period Minimization with Multiple Wave Propation," Proceedings of the 28th ACM/IEEE Design Automation Conference, pp. 640-643, Jun. 17-21, 1991.
S. F. Anderson, et al., "The IBM System/360 Model 91: Floating-Point Execution Unit," IBM J. of research and development, vol. 11, No. 1, pp. 34-53, Jan., 1967.
F. Klass, et al., "Fast Multiplication in VLSI Using Wave Pipelining Techniques," J. of VLSI Signal Processing, vol. 7, No. 3, pp. 233-248, May, 1994.
D. Fan, et al., "A CMOS Parallel Adder Using Wave Pipelining," Advanced Research in VLSI and Parallel Systems, pp. 147-164, Proceedings of the 1992 Brown/MIT Conference.
M. Flynn, et al., "Subnanosecond Arithmetic," Abstract for 1990-1993, Computer Systems Laboratory, Stanford University, pp. i-13, May, 1993.
D. Ghosh, et al., "A 400MHZ Wave-Pipelined 8.times.8 bit Multiplier in CMOS Technology," pp. 198-201 IEEE 1993.
C. Thomas Gray, et al., "Theoretical and Practical Issues in CMOS Wave Pipelining," Dept. of Electrical and Computer Engineering, North Carolina State University, Elsevier Science Publishers B.V., pp. 397-409, 1992.
F. Klass, et al. "Pushing the Limits of CMOS Technology: A Wave-Pipelined Multiplier," Hot Chips V, pp. 1-22 (Aug., 1993).
F. Klass and J. M. Mulder, "Use of CMOS Technology in Wave Pipelining," Section Computer Architecture and Digital Systems, Delft University of Technology, pp. 303-308, IEEE 1991.
Derek C. Wong, et al., "Designing High-Performance Digital Circuits Using Wave Pipelining: Alogrithms and Practical Experiences," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. 12, No. 1, pp. 25-46, Jan., 1993.
Xuguang Zhang, et al. "CMOS Wave Pipelining by Complementary Pass-Transistor Logic," Dept. of Electrical and Computer Engineering, pp. 1-12, Jul. 24, 1993.
L. W. Cotten, "Maximum-rate pipeline systems," AFIPS Conference Proceedings, 1969 Spring Joint Computer Conference, vol. 34, pp. 581-586, May 14-16, 1969.
Sheldon B. Akers, "Binary Decision Diagrams," IEEE Transactions on Computers, vol. C-27, No. 6, pp. 509-516, Jun., 1978.

Affiliated with

Also associated with

Rating

Complementary field-effect transistor logic circuits for wave pi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Complementary field-effect transistor logic circuits for wave pi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary field-effect transistor logic circuits for wave pi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-225514