Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2008-09-24
2010-06-29
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S093000, C326S096000
Reexamination Certificate
active
07746117
ABSTRACT:
A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.
REFERENCES:
patent: 5473269 (1995-12-01), Dickinson
patent: 5506519 (1996-04-01), Avery et al.
patent: 5602497 (1997-02-01), Thomas
patent: 5701093 (1997-12-01), Suzuki
Ye at al, QSERL:Quasi-static Energy Recovery Logic, Feb. 2001, IEEE Journal of Solid-State Circuits, vol. 36, No. 2, pp. 239-248.
Gong Cihun-Siyong
Hong Ci-Tong
Shiue Muh-Tian
Su Chun-Hsien
Yao Kai-Wen
Chang Gung University
Hammond Crystal L
Tan Vibol
LandOfFree
Complementary energy path adiabatic logic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Complementary energy path adiabatic logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary energy path adiabatic logic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4181513