Complementary bipolar and CMOS on SOI

Details Complementary bipolar and CMOS on SOI Complementary bipolar and CMOS on SOI

1992-03-30

1992-11-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 57, 437 59, 437 21, 148DIG150, H01L 21265

Patent

active

051643260

ABSTRACT:
A method for fabricating BiCMOS on SOI. An SOI wafer (14) with an oxide layer (17) and a nitride layer (16) has areas isolated by a LOCOS or mesa isolation (13). A region (15) is defined for CMOS structures from which the insulating layers (17,16) are removed. A gate oxide (21), a polycrystalline silicon layer (22), and a second insulating layer (23,24) is formed. A region for emitters (26) is defined and nitride deposited to form a spacer (27). An oxide layer (28) is grown over the polycrystalline silicon (22) within the emitter region (26). The wafer (14) is etched to the underlying monocrystalline silicon (18) forming base contacts (31). A polycrystalline silicon spacer (36) is formed from a second polycrystalline layer (43) and an oxide spacer (40) is deposited. A region for bipolar collectors (32) and CMOS areas (34) is defined and a spacer (38) deposited.

REFERENCES:
patent: 4777147 (1988-10-01), Scott et al.
patent: 4868135 (1989-09-01), Ogura et al.
patent: 4988638 (1991-01-01), Huang et al.
patent: 5024965 (1991-06-01), Chang et al.
patent: 5102809 (1992-04-01), Eklund et al.

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