Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-10
2007-04-10
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10896431
ABSTRACT:
Electronic system functionality can be initially implemented as software code (e.g., in programming languages such as C, C++ or Pascal) and selectively converted to a hardware representation such as in hardware description language (e.g., VHDL, Verilog, HandelC, BachC, SpecC and System Verilog). In one aspect, software code representations comprising memory dereferencing operations (e.g., related to pointers, arrays and structs) may also be converted to a hardware representation. The newly converted hardware representation may be given control of a main communications network (e.g., system bus) of the electronic system to control the execution of the memory dereferencing operations (e.g., related to pointers, arrays and structs). In one embodiment, bus control may be via a bus control interface adapted for a particular kind of communications network (e.g., a processor bus, a system bus, a hierarchical bus, a cross bar, a multiplexer bus, a switch network and a point to point network). In another embodiment, a software memory dereferencer for executing memory dereferencing operations may be provided.
REFERENCES:
patent: 6053947 (2000-04-01), Parson
patent: 6226776 (2001-05-01), Panchul et al.
patent: 6457164 (2002-09-01), Hwang et al.
patent: 6484177 (2002-11-01), Van Huben et al.
patent: 6487698 (2002-11-01), Andreev et al.
patent: 6584601 (2003-06-01), Kodosky et al.
patent: 2002/0133788 (2002-09-01), Waters et al.
patent: 2003/0074640 (2003-04-01), Mandell et al.
patent: 2003/0121010 (2003-06-01), Aubury
Ade et al., “Hardware-Software Codesign with GRAPE,”Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping, pp. 40-47 (Jun. 1995).
Elliott, J.P.,Understanding Behavioral Synthesis, “Table of Contents,” “Chapter 2: An Introduction to Behavioral Synthesis” “Chapter 3: The Behavioral Synthesis Process,” “Chapter 4: Data Types,” “Chapter 5: Entities, Architectures, and Processes,” “Chapter 10: Functions, Procedures, and Packages,” “Chapter 12: Reusable Test Benches,” “Chapter 13: Coding for Behavioral Synthesis,” “Index, ” Kluwer Academic Publishers Group, pp. v-xiv, 5-23, 25-40, 41-55, 57-76, 173-180, 197-211, 213-243, 313-319 (1999).
“Monet Interactive Architectural Exploration Through Behavioral Design,” 3pp. [Downloaded from the World Wide Web on Feb. 6, 2002.].
“Monet Technical Papers,” 1p. [Downloaded from the World Wide Web on Feb. 6, 2002.].
Elliott, J.,An Introduction to Architectural Exploration, “Part I: Introduction & Terminology,” 8pp. (Mar. 1998).
Elliott, J.,An Introduction to Architectural Exploration, “Part II: I/O Modes,” 12pp. (Apr. 1998).
Elliott, J.,An Introduction to Architectural Exploration, “Part III: Loops,” 8pp. (Apr. 1998).
Elliott, J.,An Introduction to Architectural Exploration, “Part IV: Handshaking,” 4pp. (Apr. 1998).
Elliott, J.,An Introduction to Architectural Exploration, “Part V: Reusable Test Benches,” 8pp. (Apr. 1998).
Wayne Wolf, “Object-Oriented Co-Synthesis of Distributed Embedded Systems,” Proc. ASP-DAC '95, pp. 553-558 (1995).
Lipton et al., “PDL++: An Optimizing Generator Language for Register Transfer Design,” IEEE International Symposium on Circuits and Systems, pp. 1135-1138 (1990).
Liao et al., “An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment,” Proc. DAC '97, 6pp. (1997).
De Micheli et al., “The Olympus Synthesis System,” IEEE Design & Test of Computers, vol. 7, Issue 5, pp. 37-53 (Oct. 1990).
Zhu et al., “Syntax and Semantics of the SpecC Language,” Proc. Workshop on Synthesis and System Integration of Mixed Technologies, 8 pp. (Dec. 1997).
Guido Arnout, “SystemC Standard,” Proc. DAC '00, pp. 573-577 (2000).
Semeria et al., “Methodology for Hardware/Software Co-verification in C/C++,” Proc. DAC '00, pp. 405-408 (2000).
Miscellaneous Web pages printed from CynApps World Wide Web site, 28 pp. [Downloaded from the World Wide Web on Sep. 14, 2001.].
CynApps, “CynLib™ Language Reference Manual,” Cynlib Release 1.4.0, 90 pp. [Downloaded from the World Wide Web on Sep. 14, 2001.].
CynApps, “CynLib Users Manual,” Cynlib Release Version 1.4.0, 120 pp. [Downloaded from the World Wide Web on Sep. 14, 2001.].
John Sanguinetti, “Bridging the Gap with Cynthesis,” 6 pp. [Downloaded from the World Wide Web on Sep. 14, 2001.].
Andy Goodrich, “Design by Successive Elaboration,” 12 pp. [Downloaded from the World Wide Web on Sep. 14, 2001.].
Svarstad et al., “A Model for Describing Communication between Aggregate Objects in the Specification and Design of Embedded Systems,” 9pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Mueller et al., “The Simulation Semantics of SystemC,” 7 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Siegmund et al., “SystemCSV:An Extension of SystemC for mixed Multi-Level Communication Modeling and Interface-Based System Design,” 7 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Economakos et al., “Behavioral Synthesis with SystemC,” 5 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Charest et al., “A Methodology for Interfacing Open Source SystemC with a Third Party Software,” 5 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Fin et al., “SystemC: A Homogenous Environment to Test Embedded Systems,” 6 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Fin et al., “The Use of SystemC for Design Verification and Integration Test of IP-Cores,” 5 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Agliada et al., “On the Reuse of VHDL Modules into SystemC Designs,” 5 pp. [Downloaded from the World Wide Web n Nov. 4, 2001.].
Fin et al., “Amleto: A Multi-language Environment for Functional Test Generation,” 8 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Heinz-Josef Schlebusch, “Converging SystemC with VSIA System-Level Data Types,” VSIA Member Meeting, VSIA Alliance, 16 pp. (Mar. 13, 2001). [Downloaded from the World Wide Web on Nov. 4, 2001.].
Stuart Swan, “An Introduction to System Level Modeling in SystemC 2.0,” Open SystemC Initiative, 13 pp. (May 2001). [Downloaded from the World Wide Web on Nov. 4, 2001.].
Thomas Komarek, “C Based System Level Design,” 60 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Bollano et al., “SystemC's Impact on the Development of IP Libraries,” IP2000 Europe Conference, 9 pp. (Oct. 2000). [Downloaded from the World Wide Web on Nov. 4, 2001.].
Heinz-Josef Schlebusch, “C-based Design of Systems-on-Chip: An EDA Perspective,” 45 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Gerlach et al., “System Level Design Using the SystemC Modeling Platform,” 5 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Kranen et al., “Open SystemC Initiative,” SystemC Users Forum, DAC—Jun. 2000, 74 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Transmodeling, Inc., “Systems to HDL Incrementally, SystemC” 7 pp. (Apr. 2000). [Downloaded from the World Wide Web on Nov. 4, 2001.].
“Modeling A 3D Graphics Pipeline with SystemC,” ST Microelectronics, Advanced System Technology, SNUG, 7 pp. (Mar. 15, 2000). [Downloaded from the World Wide Web on Nov. 4, 2001.].
“Overview of the Open SystemC Initiative,” 2 pp. [Downloaded from the World Wide Web on Nov. 4, 2001.].
Karen Bartleson, “A New Standard for System-Level Design,” Synopsys, 6 pp. (Sep. 1999). [Downloaded from the World Wide Web on Nov. 4, 2001.].
Jamison et al., “Connecting the Va
Klein Russell Alan
Moona Rajat
Chiang Jack
Klarquist & Sparkman, LLP
Tat Binh
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