Compiler having automatic common blocks of memory splitting

Details Compiler having automatic common blocks of memory splitting Compiler having automatic common blocks of memory splitting

1996-07-29

1998-12-08

Trammell, James P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395709, 395701, 711 3, 711118, 711122, G06F 1206, G06F 1208

Patent

active

058482750

ABSTRACT:
In a computer system having a cache memory and a main memory for storing data, a method for laying out blocks of data to minimize a number of memory transfers between the cache memory and the main memory. Memory layout normally occurs at link time, after all the source files have been compiled. The code is compiled with the assumption that the memory blocks can be optimally placed. The linker then determines whether there has been any memory violations. Memory violations are marked. All marked memory locations are then placed in a layout that satisfies adjacency requirements.

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Per Ling. "A Set of High-Performance Level 3 BLAS Structured and Tuned for the IBM 3090 VF and Implemented in Fortran 77." Sep. 1993. The Journal of Supercomputing No. 3. Boston, US.
J.E. Aull. "Validation Using CASE Tools." Apr. 5, 1992. IEEE.

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