Compiled self-resetting CMOS logic array macros

Details Compiled self-resetting CMOS logic array macros Compiled self-resetting CMOS logic array macros

1997-05-02

1999-12-21

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 97, 326121, H03K 19096

Patent

active

060054166

ABSTRACT:
A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems. The distinguishing features of SLAMs are uniquely combined to allow the automated design, from a logic description and interface specifications, of a complete macro satisfying predetermined design guidelines.

REFERENCES:
patent: 5550490 (1996-08-01), Durham et al.
patent: 5565798 (1996-10-01), Durham et al.
patent: 5828234 (1998-10-01), Sprague
patent: 5870411 (1999-02-01), Durham et al.

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