Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-21
2007-08-21
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11023592
ABSTRACT:
A system is described for managing interaction between an untimed HAL portion and a timed HDL portion of the testbench, wherein the timed portion is embodied on an emulator and the un-timed portion executes on a workstation. Repeatability of verification results may be achieved even though the HAL portion and the HDL portion run in parallel with each other. A communication interface is also described for synchronizing and passing data between multiple HDL threads on the emulator domain and simultaneously-running multiple HAL threads on the workstation domain. In addition, a remote procedural-call-based communication link, transparent to the user, is generated between the workstation and the emulator. A technique provides for repeatability for blocking and non-blocking procedure calls. FSMs and synchronization logic are automatically inferred to implement remote procedural calls. A subset of behavioral language is identified that combines the power of conventional modeling paradigms with RTL performance.
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Badaya Yogesh
Banerjee Kingshuk
Gupta Sanjay
Krishnamurthy Suresh
Kulshrestha Vipul
Banner & Witcoff , Ltd.
Garbowski Leigh M.
Mentor Graphics Corporation
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