Compilation in a high-level modeling system

Details Compilation in a high-level modeling system Compilation in a high-level modeling system

2006-07-25

2006-07-25

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07082594

ABSTRACT:
Methods and apparatus are disclosed for compiling high-level blocks of an electronic hardware design in a high-level modeling system (HLMS) into hardware description language (HDL) components. Clock requirements are established, along with (optionally) explicit connections from implicit connections between the high-level blocks. In one pass through the high-level blocks, HDL components are generated that are consistent with the clock requirements and explicit connections, if any.

REFERENCES:
patent: 6823497 (2004-11-01), Schubert et al.

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