Compensation techniques for reducing power consumption in...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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C327S540000, C327S362000, C327S378000

Reexamination Certificate

active

07965133

ABSTRACT:
A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

REFERENCES:
patent: 5337254 (1994-08-01), Knee et al.
patent: 7551020 (2009-06-01), Bhattacharya et al.
patent: 2002/0030521 (2002-03-01), Mizuno et al.
patent: 2004/0183588 (2004-09-01), Chandrakasan et al.
patent: PCT/US2007/083168 (2008-07-01), None
D. Ernst et al., “Razor: A low-Power Pipeline Based on Circuit-Level Timing Speculation, ” IEEE, Proceedings of the 36th International Symposium on Microarchitecture, Dec. 2003, pp. 7-18.
H. Kaul et al., “DVS for On-Chip Bus Designs Based on Timing Error Correction,” IEEE, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Mar. 2005, pp. 80-85.

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