Compensating delay element for clock generation in a memory devi

Details Compensating delay element for clock generation in a memory devi Compensating delay element for clock generation in a memory devi

1993-12-20

1995-06-13

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Signals

365233, G11C 1300

Patent

active

054249856

ABSTRACT:
Circuits and methods for generating a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device is disclosed. In a first embodiment, a delay circuit is provided for generating an output clock signal for controlling a circuit internal to an integrated circuit, such as a clocked sense amplifier in a memory device, relative to an earlier timing signal, such as a row select signal. The delay circuit is implemented by components having their design parameters, such as transistor dimensions and transistor orientation, corresponding to elements in an active portion of the circuit, such as memory cell transistors. Process variations that affect the electrical properties and the speed of the transistors in the active portion of the circuit will similarly affect the electrical properties and speed of transistors in the delay circuit, so the delay circuit can track and automatically compensate for process-induced speed variations, eliminating the need for large design time margins. Alternative embodiments are also disclosed which account for the threshold voltage drops across pass transistors in a memory array, and mimic the memory cell read current, when generating a sense amplifier clock signal.

REFERENCES:
patent: 4710902 (1987-12-01), Pelley, III et al.
patent: 4800304 (1989-01-01), Takeuchi
patent: 4841488 (1989-06-01), Sanada
patent: 4866675 (1989-09-01), Kawashima

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