Compensating a long read time of a memory device in data...

Details Compensating a long read time of a memory device in data... Compensating a long read time of a memory device in data...

2007-08-28

2007-08-28

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Parallel read/write

C365S219000

Reexamination Certificate

active

10565149

ABSTRACT:
A memory device is disclosed that has a longer read time than write time and implements a parallel-read operation. The parallel-read operation saves reading time and thus accelerates a write operation that comprises a step of comparing incoming data with memory data that were stored in the memory before. The arrangement is especially applicable to an MRAM memory with 0T1MTJ memory cells. The parallel-read operation involves reading in parallel a large amount of data or all data to be compared from the memory into a first temporary memory. The write data is stored in a second temporary memory. The memory data contained in the first temporary memory is compared with the corresponding write data contained in the second temporary memory and allocated to the same address information. Only that write data is written to the memory, which is different from the corresponding memory data.

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