Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-25
2003-10-28
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S592000
Reexamination Certificate
active
06639284
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of integrated circuits, and is more specifically directed to electrostatic discharge protection devices in modern integrated circuits.
Modern high-density integrated circuits are known to be vulnerable to damage from the electrostatic discharge (ESD) of a charged body (human or otherwise) that physically contacts the integrated circuit. ESD damage occurs when the amount of charge exceeds the capability of the conduction path through the integrated circuit. The typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate-junction shorting (e.g., in the metal-oxide-semiconductor, or MOS, context).
To avoid damage from ESD, modern integrated circuits incorporate ESD protection devices at each external terminal. ESD protection devices generally operate by providing a high capacity conduction path for the brief but massive ESD charge, safely conducting this energy away from other structures that are not capable of handling the event. In some cases, ESD protection is inherent to the particular terminal, as in the case of a power supply terminal which may provide an extremely large p-n junction that can absorb the ESD charge. Inputs and outputs, on the other hand, typically have a specific ESD protection device added in parallel with the functional terminal. The ideal ESD protection device turns on quickly in response to an ESD event, with large conduction capability, but remains off and presents no load during normal operation.
Examples of ESD protection devices are well known in the art. In the case of MOS technology, an early ESD protection device was provided by a parasitic thick-field oxide MOS transistor that was turned on by and conducted ESD current, as described in U.S. Pat. No. 4,692,781 and in U.S. Pat. No. 4,855,620, both assigned to Texas Instruments Incorporated and incorporated herein by this reference.
As the feature sizes of MOS integrated circuits became smaller, and with the advent of complementary MOS (CMOS) technology, the most popular ESD protection devices utilized a parasitic bipolar device to conduct the ESD current, triggered by way of a silicon-controlled-rectifier (SCR) structure. SCRs are very robust devices, as they can repeatedly conduct relatively large transient currents without being vulnerable to irreversible breakdown damage and the like. The CMOS parasitic SCR is formed by way of a p-type source/drain region serving as the SCR anode, an n-type source/drain region serving as the SCR cathode, and corresponding n-type and p-type wells serving as the bases of the parasitic p-n-p and n-p-n bipolar transistors. Examples of a CMOS parasitic SCR protection device is described in Rountree et al., “A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes”, 1988
EOS/ESD Symposium
, pp. 201-205, and in U.S. Pat. No. 5,012,317 assigned to Texas Instruments Incorporated, both incorporated herein by this reference.
FIG. 1
a
illustrates, in cross-section, an example of this conventional CMOS parasitic SCR ESD protection device in an integrated circuit. In this example, the structure is formed at a surface of p-type substrate
10
, which has n-well
12
formed at a surface. Isolation oxide structures
15
, which in this case are field oxide structures formed by conventional LOCOS (local oxidation of silicon), define the active regions of the surface, at which n+ regions
14
,
20
, and p+ region
16
are formed by masked ion implant. In this arrangement, the anode of the protection device is region
16
, which is connected to terminal
18
, typically a bond pad for receiving an external connection of the integrated circuit when packaged. N+ region
14
is also formed in n-well
12
along with p+ region
16
, and is connected to terminal
18
to ensure that the p-n junction between p+ region
16
and n-well
12
is not forward biased in normal operation. In some cases, for example at CMOS push-pull outputs, n+ region
14
may instead be tied to a power supply (V
cc
) bus of the integrated circuit, rather than to terminal
18
. The cathode of the structure is n+ region
20
, which is connected to ground in the integrated circuit. In the ESD context, the integrated circuit is not biased to power supply voltages or system ground, and as such the ground connection to n+ region
20
is established by the connection of this region to one or more large doped regions in the integrated circuit, sufficiently large to serve as a sink for the charge received in an ESD event. In operation, as described in U.S. Pat. No. 5,012,317, a positive polarity ESD event received at terminal
18
and applied to regions
14
,
16
will forward bias the p-n junction between p+ region
16
and n-well
12
, and eventually cause the junction between n-well
12
and p substrate
10
to enter avalanche breakdown. Electrons generated by this avalanche breakdown provide the initial base current for the p-n-p device, and holes generated by this avalanche breakdown provide the initial base current for the n-p-n device. The parasitic p-n-p transistor formed by p+ region
16
(emitter), n-well
12
(base), and p substrate
10
(collector) will then turn on, providing base current to the parasitic lateral n-p-n transistor formed by n+ region
14
and n-well
12
(collector), p substrate
10
(base) and n+ region
20
(emitter). Likewise, the n-p-n device will turn on, providing base current to the p-n-p device. These two parasitic bipolar devices operate as an SCR, and safely conduct the current from the ESD event to the cathode (n+ region
20
), preventing damage to functional circuitry connected to terminal
18
.
By way of further background, several improvements and modifications have been made over the years to the CMOS SCR protection device design. The SCR breakdown voltage has been reduced by including an n-type source/drain diffusion straddling the well boundary, as described in U.S. Pat. No. 4,939,616, assigned to Texas Instruments Incorporated and incorporated herein by this reference. An example of this structure, commonly referred to as a low voltage SCR (LVSCR), is shown in
FIG. 1
b
. The structure of
FIG. 1
b
is constructed similarly to that of
FIG. 1
a
, but includes an additional n+ region
22
that straddles the boundary of n-well
12
. N+ region
22
is effectively resistively connected to terminal
18
, with the resistance established by portions of n-well
12
near terminal
18
. As described in U.S. Pat. No. 4,939,616, n+ region
22
in the structure of
FIG. 1
b
assists the triggering of the SCR, because of the reduced avalanche breakdown voltage at the junction between relatively heavily doped n+ region
22
and p substrate
10
, as compared with the breakdown voltage at the junction between lightly-doped n-well
12
and lightly-doped p substrate
10
.
U.S. Pat. No. 5,465,189, assigned to Texas Instruments Incorporated and incorporated herein by this reference, describes a CMOS SCR (commonly referred as the “LVTSCR”) in which the n-type source/drain region straddling the well boundary is gated. An example of a structure according to this approach is shown, in cross-section, in
FIG. 1
c
. In this example, n+ region
22
straddles the boundary of n-well
12
as in the case of
FIG. 1
b
. Polysilicon electrode
26
is disposed between n+ region
22
and n+ region
20
(which is outside of n-well
12
), overlying gate dielectric
24
, thus forming an MOS transistor. Gate electrode
26
is connected to ground, either directly, as shown, or alternatively through a resistor, as described in U.S. Pat. No. 5,907,462. N+ region
20
is also connected to ground. As described in U.S. Pat. No. 5,465,189, this gated device effectively defines a desired low SCR trigger voltage.
U.S. Pat. No. 5,907,462, assigned
Chatterjee Amitava
Kunz Keith E.
Brady III W. James
Garner Jacqueline J.
Prenty Mark V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Compensated-well electrostatic discharge protection structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Compensated-well electrostatic discharge protection structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compensated-well electrostatic discharge protection structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3136746